x86/cpu/amd: Correct the microcode table for Zenbleed

The good revisions are tied to exact steppings, meaning it's not valid to
match on model number alone, let alone a range.

This is probably only a latent issue.  From public microcode archives, the
following CPUs exist 17-30-00, 17-60-00, 17-70-00 and would be captured by the
model ranges.  They're likely pre-production steppings, and likely didn't get
Zenbleed microcode, but it's still incorrect to compare them to a different
steppings revision.

Either way, convert the logic to use x86_match_min_microcode_rev(), which is
the preferred mechanism.

Fixes: 522b1d69219d ("x86/cpu/amd: Add a Zenbleed fix")
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: x86@kernel.org
Link: https://patch.msgid.link/20251126130352.880424-1-andrew.cooper3@citrix.com

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index bc94ff1e250ad2dc217e8e7c926e2af4a61fb7a3..86059f2c0fcd45c0405e7f623d86769c4c90f79f 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -951,26 +951,14 @@ static void init_amd_zen1(struct cpuinfo_x86 *c)
        }
 }
 
-static bool cpu_has_zenbleed_microcode(void)
-{
-       u32 good_rev = 0;
-
-       switch (boot_cpu_data.x86_model) {
-       case 0x30 ... 0x3f: good_rev = 0x0830107b; break;
-       case 0x60 ... 0x67: good_rev = 0x0860010c; break;
-       case 0x68 ... 0x6f: good_rev = 0x08608107; break;
-       case 0x70 ... 0x7f: good_rev = 0x08701033; break;
-       case 0xa0 ... 0xaf: good_rev = 0x08a00009; break;
-
-       default:
-               return false;
-       }
-
-       if (boot_cpu_data.microcode < good_rev)
-               return false;
-
-       return true;
-}
+static const struct x86_cpu_id amd_zenbleed_microcode[] = {
+       ZEN_MODEL_STEP_UCODE(0x17, 0x31, 0x0, 0x0830107b),
+       ZEN_MODEL_STEP_UCODE(0x17, 0x60, 0x1, 0x0860010c),
+       ZEN_MODEL_STEP_UCODE(0x17, 0x68, 0x1, 0x08608107),
+       ZEN_MODEL_STEP_UCODE(0x17, 0x71, 0x0, 0x08701033),
+       ZEN_MODEL_STEP_UCODE(0x17, 0xa0, 0x0, 0x08a00009),
+       {}
+};
 
 static void zen2_zenbleed_check(struct cpuinfo_x86 *c)
 {
@@ -980,7 +968,7 @@ static void zen2_zenbleed_check(struct cpuinfo_x86 *c)
        if (!cpu_has(c, X86_FEATURE_AVX))
                return;
 
-       if (!cpu_has_zenbleed_microcode()) {
+       if (!x86_match_min_microcode_rev(amd_zenbleed_microcode)) {
                pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");
                msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
        } else {