Daily bump.

diff --git a/ChangeLog b/ChangeLog
index 9e9efe7ac3121f470ca9e0eaee3846d84578cf24..46466e76b1851c8afd18f7863b1b8f339a42be44 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2026-01-05  Filip Kastl  <fkastl@suse.cz>
+
+       * MAINTAINERS: Put <jeffrey.law@oss.qualcomm.com> before
+       <jeffreyalaw@gmail.com>.
+
 2025-12-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
        * Makefile.def (flags_to_pass): Rename GA68, GA68FLAGS,

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7c92bf6e291d4834ea26a63b50b2698eea6ea8ea..f3c5238e8b1aa88a0cce8c5e3a95e164fcd192d1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,94 @@
+2026-01-05  Tamar Christina  <tamar.christina@arm.com>
+
+       PR tree-optimization/122103
+       * tree-vect-stmts.cc (vectorizable_call): Handle trapping math.
+
+2026-01-05  Tamar Christina  <tamar.christina@arm.com>
+
+       PR tree-optimization/122103
+       * tree-if-conv.cc (ifcvt_can_predicate): Support gimple_call_builtin_p.
+       (if_convertible_stmt_p, predicate_rhs_code,
+       predicate_statements): Likewise.
+
+2026-01-05  Tamar Christina  <tamar.christina@arm.com>
+
+       PR tree-optimization/122103
+       * match.pd: Add COND_FMA to COND_FMS rewrite rules.
+
+2026-01-05  Tamar Christina  <tamar.christina@arm.com>
+
+       PR tree-optimization/122103
+       * doc/md.texi: Document them
+       * internal-fn.cc (FOR_EACH_COND_FN_PAIR, internal_fn_else_index): Add
+       SQRT, CEIL, FLOOR, ROUND and RINT.
+       * internal-fn.def (IFN_COND_SQRT, IFN_COND_CEIL, IFN_COND_FLOOR,
+       IFN_COND_ROUND, IFN_COND_RINT, IFN_COND_LEN_SQRT, IFN_COND_LEN_CEIL,
+       IFN_COND_LEN_FLOOR, IFN_COND_LEN_ROUND, IFN_COND_LEN_RINT): New.
+       * optabs.def (cond_rint_optab, cond_sqrt_optab, cond_round_optab,
+       cond_ceil_optab, cond_floor_optab, cond_len_rint_optab,
+       cond_len_sqrt_optab, cond_len_round_optab, cond_len_ceil_optab,
+       cond_len_floor_optab): New.
+
+2026-01-05  Tamar Christina  <tamar.christina@arm.com>
+
+       PR tree-optimization/122103
+       * gimple.cc (gimple_could_trap_p_1): Handle __builtin_ calls.
+
+2026-01-05  Jeff Law  <jeffrey.law@oss.qualcomm.com>
+
+       * config/riscv/riscv-string.cc (expand_block_move): Restore using
+       inlined memcpy/memmove for unknown counts if the param hasn't been
+       specified.
+       (expand_vec_setmem): Similarly for memset.
+
+2026-01-05  Pan Li  <pan2.li@intel.com>
+
+       PR target/123317
+       * config/riscv/autovec-opt.md: Take zero_extend for
+       both the vwaddu and vwsubu wx pattern.
+
+2026-01-05  Alice Carlotti  <alice.carlotti@arm.com>
+
+       * config/aarch64/aarch64-sme.md
+       (aarch64_sme_write_zt): Add TARGET_STREAMING requirement.
+       (aarch64_sme_lut_zt): Ditto.
+
+2026-01-05  Alice Carlotti  <alice.carlotti@arm.com>
+
+       * doc/invoke.texi: Fix incorrect function name.
+
+2026-01-05  Pan Li  <pan2.li@intel.com>
+
+       * tree-vect-slp.cc (vec_slp_has_scalar_use): Adjust the
+       depth_limit from 2 to 3.
+
+2026-01-05  Tamar Christina  <tamar.christina@arm.com>
+
+       PR target/121290
+       * config/aarch64/aarch64.cc (aarch64_possible_by_lane_insn_p): New.
+       (aarch64_vector_costs): Add m_num_dup_stmts and m_num_total_stmts.
+       (aarch64_vector_costs::add_stmt_cost): Use them.
+       (adjust_body_cost): Likewise.
+
+2026-01-05  Tamar Christina  <tamar.christina@arm.com>
+
+       PR target/123017
+       * config/aarch64/aarch64-json-schema.h: Add br_mispredict_factor.
+       * config/aarch64/aarch64-json-tunings-parser-generated.inc
+       (parse_branch_costs): Add br_mispredict_factor.
+       * config/aarch64/aarch64-json-tunings-printer-generated.inc
+       (serialize_branch_costs): Add br_mispredict_factor.
+       * config/aarch64/aarch64-protos.h (struct cpu_branch_cost): Add
+       br_mispredict_factor.
+       * config/aarch64/aarch64.cc (aarch64_max_noce_ifcvt_seq_cost,
+       aarch64_noce_conversion_profitable_p,
+       TARGET_MAX_NOCE_IFCVT_SEQ_COST,
+       TARGET_NOCE_CONVERSION_PROFITABLE_P): New.
+       * config/aarch64/tuning_models/generic.h (generic_branch_cost): Add
+       br_mispredict_factor.
+       * config/aarch64/tuning_models/generic_armv8_a.h: Remove
+       generic_armv8_a_branch_cost and use generic_branch_cost.
+
 2026-01-04  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
 
        * configure: Regenerate.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2a4d02b831b1b365663a206bed456146fc6eaa7e..94d087a56f7ca40e29159fbc0711c42df14a5183 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20260105
+20260106

diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index f39837696a3b2cd9c7f1cf6069006d202aaf7ec1..b8615ed722155231431e77ba1100e67c9a0b0393 100644 (file)
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,19 @@
+2026-01-05  Paul Thomas  <pault@gcc.gnu.org>
+
+       PR fortran/123071
+       * resolve.cc (resolve_typebound_function): Make sure that the
+       class declared type is resolved.
+       (resolve_allocate_deallocate): Any kind of expr3 array ref will
+       need resolution not just constant size refs.
+       * trans-decl.cc (gfc_trans_deferred_vars): Exclude vtabs from
+       initialization.
+       (emit_not_set_warning): New function using code extracted from
+       gfc_generate_function_code.
+       (gfc_generate_function_code): PDT module procedures results
+       that have not been referenced must have the fake_result_decl
+       added to the symbol and emit_not_set_warning called. Likewise
+       replace explicit code with call to emit_not_set_warning.
+
 2026-01-03  Paul Thomas  <pault@gcc.gnu.org>
 
        PR fortran/123352

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d7939fe5ebf142cb073537b1662d8a903185f62e..06ab68f835d57fca59b1de69c60e9f0928a9e5a9 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,79 @@
+2026-01-05  Tamar Christina  <tamar.christina@arm.com>
+
+       PR tree-optimization/122103
+       * gcc.target/aarch64/sve/pr122103_4.c: New test.
+       * gcc.target/aarch64/sve/pr122103_5.c: New test.
+       * gcc.target/aarch64/sve/pr122103_6.c: New test.
+
+2026-01-05  Tamar Christina  <tamar.christina@arm.com>
+
+       PR tree-optimization/122103
+       * gcc.target/aarch64/sve/pr122103_1.c: New test.
+       * gcc.target/aarch64/sve/pr122103_2.c: New test.
+       * gcc.target/aarch64/sve/pr122103_3.c: New test.
+
+2026-01-05  Tamar Christina  <tamar.christina@arm.com>
+
+       PR tree-optimization/122103
+       * gcc.target/aarch64/sve/unpacked_frinta_1.c: Add -fno-trapping-math.
+       * gcc.target/aarch64/sve/unpacked_frinti_1.c: Likewise.
+       * gcc.target/aarch64/sve/unpacked_frintm_1.c: Likewise.
+       * gcc.target/aarch64/sve/unpacked_frintp_1.c: Likewise.
+       * gcc.target/aarch64/sve/unpacked_frintx_1.c: Likewise.
+       * gcc.target/aarch64/sve/unpacked_frintz_1.c: Likewise.
+       * gcc.target/aarch64/sve/unpacked_cond_frinta_2.c: Likewise.
+       * gcc.target/aarch64/sve/vcond_13.c: Likewise.
+       * gcc.target/aarch64/sve/vcond_14.c: Likewise.
+       * gcc.target/aarch64/sve/vcond_15.c: Likewise.
+       * gcc.target/aarch64/sve/vcond_16.c: Likewise.
+       * gcc.target/i386/avx-pr93078.c: Likewise.
+       * gcc.target/i386/avx512f-pr93078.c: Likewise.
+
+2026-01-05  Pan Li  <pan2.li@intel.com>
+
+       PR target/123317
+       * gcc.target/riscv/rvv/autovec/pr123317-run-1.c: New test.
+       * gcc.target/riscv/rvv/autovec/pr123317-run-2.c: New test.
+       * gcc.target/riscv/rvv/autovec/pr123317-run-3.c: New test.
+       * gcc.target/riscv/rvv/autovec/pr123317-run-4.c: New test.
+       * gcc.target/riscv/rvv/autovec/pr123317-run.h: New test.
+
+2026-01-05  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Adjust the
+       asm check.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto.
+       * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
+
+2026-01-05  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/rvv/autovec/sat_add-cost-1.c: New test.
+
+2026-01-05  Tamar Christina  <tamar.christina@arm.com>
+
+       PR target/121290
+       * gcc.target/aarch64/pr121290.c: Move to...
+       * gcc.target/aarch64/pr121290_1.c: ...here.
+       * g++.target/aarch64/pr121290_1.C: New test.
+       * gcc.target/aarch64/pr121290_2.c: New test.
+
+2026-01-05  Tamar Christina  <tamar.christina@arm.com>
+
+       PR target/123017
+       * gcc.target/aarch64/pr123017_1.c: New test.
+       * gcc.target/aarch64/pr123017_2.c: New test.
+       * gcc.target/aarch64/pr123017_3.c: New test.
+       * gcc.target/aarch64/pr123017_4.c: New test.
+       * gcc.target/aarch64/pr123017_5.c: New test.
+       * gcc.target/aarch64/pr123017_6.c: New test.
+       * gcc.target/aarch64/pr123017_7.c: New test.
+
+2026-01-05  Paul Thomas  <pault@gcc.gnu.org>
+
+       PR fortran/123071
+       * gfortran.dg/pdt_79.f03: New test.
+
 2026-01-04  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
 
        PR testsuite/123377

diff --git a/libcpp/po/ChangeLog b/libcpp/po/ChangeLog
index 99d0fb4fb6ced3f1064b3c34439766969e31a6a6..5bb482560a611552c38a8c9614e4bc1014fd1b43 100644 (file)
--- a/libcpp/po/ChangeLog
+++ b/libcpp/po/ChangeLog
@@ -1,3 +1,7 @@
+2026-01-05  Joseph Myers  <josmyers@redhat.com>
+
+       * ka.po: Update.
+
 2025-07-30  Joseph Myers  <josmyers@redhat.com>
 
        * sr.po: Update.