/* Disable forwarding by default on all ports */
mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
-@@ -2550,8 +2553,10 @@ mt7531_setup_common(struct dsa_switch *d
+@@ -2553,8 +2556,10 @@ mt7531_setup_common(struct dsa_switch *d
/* Clear link settings and enable force mode to force link down
* on all ports until they're enabled later.
*/
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -16870,6 +16870,13 @@ F: drivers/pinctrl/
+@@ -16872,6 +16872,13 @@ F: drivers/pinctrl/
F: include/dt-bindings/pinctrl/
F: include/linux/pinctrl/
--- a/drivers/net/phy/microchip.c
+++ b/drivers/net/phy/microchip.c
-@@ -233,6 +233,7 @@ static int lan88xx_probe(struct phy_devi
+@@ -192,6 +192,7 @@ static int lan88xx_probe(struct phy_devi
struct device *dev = &phydev->mdio.dev;
struct lan88xx_priv *priv;
u32 led_modes[4];
int len;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-@@ -262,6 +263,32 @@ static int lan88xx_probe(struct phy_devi
+@@ -221,6 +222,32 @@ static int lan88xx_probe(struct phy_devi
return -EINVAL;
}
if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
-@@ -3715,6 +3715,48 @@ static int xhci_align_td(struct xhci_hcd
+@@ -3718,6 +3718,48 @@ static int xhci_align_td(struct xhci_hcd
return 1;
}
/* This is very similar to what ehci-q.c qtd_fill() does */
int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
struct urb *urb, int slot_id, unsigned int ep_index)
-@@ -3871,6 +3913,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3874,6 +3916,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
}
check_trb_math(urb, enqd_len);
giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
start_cycle, start_trb);
return 0;
-@@ -4020,6 +4064,8 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
+@@ -4023,6 +4067,8 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
/* Event on completion */
field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
-@@ -967,9 +967,6 @@ static int pci_register_host_bridge(stru
+@@ -969,9 +969,6 @@ static int pci_register_host_bridge(stru
else
pr_info("PCI host bridge to bus %s\n", name);
mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
if (mtk_is_netsys_v3_or_greater(eth)) {
-@@ -5037,11 +5037,15 @@ static const struct mtk_soc_data mt2701_
+@@ -5053,11 +5053,15 @@ static const struct mtk_soc_data mt2701_
.required_clks = MT7623_CLKS_BITMAP,
.required_pctl = true,
.version = 1,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5057,11 +5061,15 @@ static const struct mtk_soc_data mt7621_
+@@ -5073,11 +5077,15 @@ static const struct mtk_soc_data mt7621_
.offload_version = 1,
.hash_offset = 2,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5079,11 +5087,15 @@ static const struct mtk_soc_data mt7622_
+@@ -5095,11 +5103,15 @@ static const struct mtk_soc_data mt7622_
.hash_offset = 2,
.has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5100,11 +5112,15 @@ static const struct mtk_soc_data mt7623_
+@@ -5116,11 +5128,15 @@ static const struct mtk_soc_data mt7623_
.hash_offset = 2,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
.disable_pll_modes = true,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5119,11 +5135,15 @@ static const struct mtk_soc_data mt7629_
+@@ -5135,11 +5151,15 @@ static const struct mtk_soc_data mt7629_
.required_pctl = false,
.has_accounting = true,
.version = 1,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5141,11 +5161,15 @@ static const struct mtk_soc_data mt7981_
+@@ -5157,11 +5177,15 @@ static const struct mtk_soc_data mt7981_
.hash_offset = 4,
.has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8,
},
-@@ -5163,11 +5187,15 @@ static const struct mtk_soc_data mt7986_
+@@ -5179,11 +5203,15 @@ static const struct mtk_soc_data mt7986_
.hash_offset = 4,
.has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8,
},
-@@ -5185,11 +5213,15 @@ static const struct mtk_soc_data mt7988_
+@@ -5201,11 +5229,15 @@ static const struct mtk_soc_data mt7988_
.hash_offset = 4,
.has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8,
},
-@@ -5202,11 +5234,15 @@ static const struct mtk_soc_data rt5350_
+@@ -5218,11 +5250,15 @@ static const struct mtk_soc_data rt5350_
.required_clks = MT7628_CLKS_BITMAP,
.required_pctl = false,
.version = 1,
},
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -327,8 +327,8 @@
+@@ -335,8 +335,8 @@
/* QDMA descriptor txd3 */
#define TX_DMA_OWNER_CPU BIT(31)
#define TX_DMA_LS0 BIT(30)
#define TX_DMA_SWC BIT(14)
#define TX_DMA_PQID GENMASK(3, 0)
#define TX_DMA_ADDR64_MASK GENMASK(3, 0)
-@@ -348,8 +348,8 @@
+@@ -356,8 +356,8 @@
/* QDMA descriptor rxd2 */
#define RX_DMA_DONE BIT(31)
#define RX_DMA_LSO BIT(30)
#define RX_DMA_VTAG BIT(15)
#define RX_DMA_ADDR64_MASK GENMASK(3, 0)
#if IS_ENABLED(CONFIG_64BIT)
-@@ -1153,10 +1153,9 @@ struct mtk_reg_map {
+@@ -1161,10 +1161,9 @@ struct mtk_reg_map {
* @foe_entry_size Foe table entry size.
* @has_accounting Bool indicating support for accounting of
* offloaded flows.
* @dma_max_len Max DMA tx/rx buffer length.
* @dma_len_offset Tx/Rx DMA length field offset.
*/
-@@ -1174,13 +1173,17 @@ struct mtk_soc_data {
+@@ -1182,13 +1181,17 @@ struct mtk_soc_data {
bool has_accounting;
bool disable_pll_modes;
struct {
/* Set FE to PDMAv2 if necessary */
val = mtk_r32(eth, MTK_FE_GLO_MISC);
mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
-@@ -5167,11 +5167,11 @@ static const struct mtk_soc_data mt7981_
+@@ -5183,11 +5183,11 @@ static const struct mtk_soc_data mt7981_
.dma_len_offset = 8,
},
.rx = {
},
};
-@@ -5193,11 +5193,11 @@ static const struct mtk_soc_data mt7986_
+@@ -5209,11 +5209,11 @@ static const struct mtk_soc_data mt7986_
.dma_len_offset = 8,
},
.rx = {
.pse_oq_sta = 0x01a0,
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -1132,7 +1132,7 @@ struct mtk_reg_map {
+@@ -1140,7 +1140,7 @@ struct mtk_reg_map {
u32 gdm1_cnt;
u32 gdma_to_ppe;
u32 ppe_base;
}
static bool mtk_hw_reset_check(struct mtk_eth *eth)
-@@ -5045,11 +5055,14 @@ static const struct mtk_soc_data mt2701_
+@@ -5061,11 +5071,14 @@ static const struct mtk_soc_data mt2701_
.desc_size = sizeof(struct mtk_tx_dma),
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5069,11 +5082,14 @@ static const struct mtk_soc_data mt7621_
+@@ -5085,11 +5098,14 @@ static const struct mtk_soc_data mt7621_
.desc_size = sizeof(struct mtk_tx_dma),
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5095,11 +5111,14 @@ static const struct mtk_soc_data mt7622_
+@@ -5111,11 +5127,14 @@ static const struct mtk_soc_data mt7622_
.desc_size = sizeof(struct mtk_tx_dma),
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5120,11 +5139,14 @@ static const struct mtk_soc_data mt7623_
+@@ -5136,11 +5155,14 @@ static const struct mtk_soc_data mt7623_
.desc_size = sizeof(struct mtk_tx_dma),
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5143,11 +5165,14 @@ static const struct mtk_soc_data mt7629_
+@@ -5159,11 +5181,14 @@ static const struct mtk_soc_data mt7629_
.desc_size = sizeof(struct mtk_tx_dma),
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5169,6 +5194,8 @@ static const struct mtk_soc_data mt7981_
+@@ -5185,6 +5210,8 @@ static const struct mtk_soc_data mt7981_
.desc_size = sizeof(struct mtk_tx_dma_v2),
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8,
},
.rx = {
.desc_size = sizeof(struct mtk_rx_dma),
-@@ -5176,6 +5203,7 @@ static const struct mtk_soc_data mt7981_
+@@ -5192,6 +5219,7 @@ static const struct mtk_soc_data mt7981_
.dma_l4_valid = RX_DMA_L4_VALID_V2,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
};
-@@ -5195,6 +5223,8 @@ static const struct mtk_soc_data mt7986_
+@@ -5211,6 +5239,8 @@ static const struct mtk_soc_data mt7986_
.desc_size = sizeof(struct mtk_tx_dma_v2),
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8,
},
.rx = {
.desc_size = sizeof(struct mtk_rx_dma),
-@@ -5202,6 +5232,7 @@ static const struct mtk_soc_data mt7986_
+@@ -5218,6 +5248,7 @@ static const struct mtk_soc_data mt7986_
.dma_l4_valid = RX_DMA_L4_VALID_V2,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
};
-@@ -5221,6 +5252,8 @@ static const struct mtk_soc_data mt7988_
+@@ -5237,6 +5268,8 @@ static const struct mtk_soc_data mt7988_
.desc_size = sizeof(struct mtk_tx_dma_v2),
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8,
},
.rx = {
.desc_size = sizeof(struct mtk_rx_dma_v2),
-@@ -5228,6 +5261,7 @@ static const struct mtk_soc_data mt7988_
+@@ -5244,6 +5277,7 @@ static const struct mtk_soc_data mt7988_
.dma_l4_valid = RX_DMA_L4_VALID_V2,
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8,
},
};
-@@ -5242,6 +5276,7 @@ static const struct mtk_soc_data rt5350_
+@@ -5258,6 +5292,7 @@ static const struct mtk_soc_data rt5350_
.desc_size = sizeof(struct mtk_tx_dma),
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
.rx = {
.desc_size = sizeof(struct mtk_rx_dma),
-@@ -5249,6 +5284,7 @@ static const struct mtk_soc_data rt5350_
+@@ -5265,6 +5300,7 @@ static const struct mtk_soc_data rt5350_
.dma_l4_valid = RX_DMA_L4_VALID_PDMA,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
#define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN)
#define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
#define MTK_DMA_DUMMY_DESC 0xffffffff
-@@ -1176,6 +1178,8 @@ struct mtk_soc_data {
+@@ -1184,6 +1186,8 @@ struct mtk_soc_data {
u32 desc_size;
u32 dma_max_len;
u32 dma_len_offset;
} tx;
struct {
u32 desc_size;
-@@ -1183,6 +1187,7 @@ struct mtk_soc_data {
+@@ -1191,6 +1195,7 @@ struct mtk_soc_data {
u32 dma_l4_valid;
u32 dma_max_len;
u32 dma_len_offset;
} rx;
};
-@@ -1264,7 +1269,7 @@ struct mtk_eth {
+@@ -1272,7 +1277,7 @@ struct mtk_eth {
struct napi_struct rx_napi;
void *scratch_ring;
dma_addr_t phy_scratch_ring;
mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
-@@ -4957,23 +4982,24 @@ static int mtk_probe(struct platform_dev
+@@ -4973,23 +4998,24 @@ static int mtk_probe(struct platform_dev
}
if (eth->soc->offload_version) {
}
for (i = 0; i < MTK_MAX_DEVS; i++) {
-@@ -5076,6 +5102,7 @@ static const struct mtk_soc_data mt7621_
+@@ -5092,6 +5118,7 @@ static const struct mtk_soc_data mt7621_
.required_pctl = false,
.version = 1,
.offload_version = 1,
.hash_offset = 2,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
.tx = {
-@@ -5104,6 +5131,7 @@ static const struct mtk_soc_data mt7622_
+@@ -5120,6 +5147,7 @@ static const struct mtk_soc_data mt7622_
.required_pctl = false,
.version = 1,
.offload_version = 2,
.hash_offset = 2,
.has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
-@@ -5132,6 +5160,7 @@ static const struct mtk_soc_data mt7623_
+@@ -5148,6 +5176,7 @@ static const struct mtk_soc_data mt7623_
.required_pctl = true,
.version = 1,
.offload_version = 1,
.hash_offset = 2,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
.disable_pll_modes = true,
-@@ -5187,6 +5216,7 @@ static const struct mtk_soc_data mt7981_
+@@ -5203,6 +5232,7 @@ static const struct mtk_soc_data mt7981_
.required_pctl = false,
.version = 2,
.offload_version = 2,
.hash_offset = 4,
.has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
-@@ -5216,6 +5246,7 @@ static const struct mtk_soc_data mt7986_
+@@ -5232,6 +5262,7 @@ static const struct mtk_soc_data mt7986_
.required_pctl = false,
.version = 2,
.offload_version = 2,
.hash_offset = 4,
.has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
-@@ -5245,6 +5276,7 @@ static const struct mtk_soc_data mt7988_
+@@ -5261,6 +5292,7 @@ static const struct mtk_soc_data mt7988_
.required_pctl = false,
.version = 3,
.offload_version = 2,
.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -1132,7 +1132,7 @@ struct mtk_reg_map {
+@@ -1140,7 +1140,7 @@ struct mtk_reg_map {
u32 tx_sch_rate; /* tx scheduler rate control registers */
} qdma;
u32 gdm1_cnt;
u32 ppe_base;
u32 wdma_base[3];
u32 pse_iq_sta;
-@@ -1170,6 +1170,7 @@ struct mtk_soc_data {
+@@ -1178,6 +1178,7 @@ struct mtk_soc_data {
u8 offload_version;
u8 hash_offset;
u8 version;
u16 foe_entry_size;
netdev_features_t hw_features;
bool has_accounting;
-@@ -1294,7 +1295,7 @@ struct mtk_eth {
+@@ -1302,7 +1303,7 @@ struct mtk_eth {
struct metadata_dst *dsa_meta[MTK_MAX_DSA_PORTS];
struct rhashtable flow_table;
struct bpf_prog __rcu *prog;
-@@ -1319,6 +1320,7 @@ struct mtk_eth {
+@@ -1327,6 +1328,7 @@ struct mtk_eth {
struct mtk_mac {
int id;
phy_interface_t interface;
int speed;
struct device_node *of_node;
struct phylink *phylink;
-@@ -1440,7 +1442,7 @@ int mtk_gmac_sgmii_path_setup(struct mtk
+@@ -1448,7 +1450,7 @@ int mtk_gmac_sgmii_path_setup(struct mtk
int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4462,6 +4462,20 @@ static int mtk_set_rxnfc(struct net_devi
+@@ -4478,6 +4478,20 @@ static int mtk_set_rxnfc(struct net_devi
return ret;
}
static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb,
struct net_device *sb_dev)
{
-@@ -4490,8 +4504,10 @@ static const struct ethtool_ops mtk_etht
+@@ -4506,8 +4520,10 @@ static const struct ethtool_ops mtk_etht
.get_strings = mtk_get_strings,
.get_sset_count = mtk_get_sset_count,
.get_ethtool_stats = mtk_get_ethtool_stats,
mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK;
mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
}
-@@ -4476,6 +4486,61 @@ static int mtk_set_pauseparam(struct net
+@@ -4492,6 +4502,61 @@ static int mtk_set_pauseparam(struct net
return phylink_ethtool_set_pauseparam(mac->phylink, pause);
}
static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb,
struct net_device *sb_dev)
{
-@@ -4508,6 +4573,8 @@ static const struct ethtool_ops mtk_etht
+@@ -4524,6 +4589,8 @@ static const struct ethtool_ops mtk_etht
.set_pauseparam = mtk_set_pauseparam,
.get_rxnfc = mtk_get_rxnfc,
.set_rxnfc = mtk_set_rxnfc,
};
static const struct net_device_ops mtk_netdev_ops = {
-@@ -4568,6 +4635,8 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4584,6 +4651,8 @@ static int mtk_add_mac(struct mtk_eth *e
}
mac = netdev_priv(eth->netdev[id]);
eth->mac[id] = mac;
mac->of_node = np;
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -453,6 +453,8 @@
+@@ -461,6 +461,8 @@
#define MAC_MCR_RX_FIFO_CLR_DIS BIT(12)
#define MAC_MCR_BACKOFF_EN BIT(9)
#define MAC_MCR_BACKPR_EN BIT(8)
#define MAC_MCR_FORCE_RX_FC BIT(5)
#define MAC_MCR_FORCE_TX_FC BIT(4)
#define MAC_MCR_SPEED_1000 BIT(3)
-@@ -461,6 +463,15 @@
+@@ -469,6 +471,15 @@
#define MAC_MCR_FORCE_LINK BIT(0)
#define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE)
/* Mac status registers */
#define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
#define MAC_MSR_EEE1G BIT(7)
-@@ -1321,6 +1332,8 @@ struct mtk_mac {
+@@ -1329,6 +1340,8 @@ struct mtk_mac {
int id;
phy_interface_t interface;
u8 ppe_idx;
default:
return "unknown";
}
-@@ -2695,6 +2681,12 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2698,6 +2684,12 @@ mt7531_setup(struct dsa_switch *ds)
return -ENODEV;
}
/* all MACs must be forced link-down before sw reset */
for (i = 0; i < MT7530_NUM_PORTS; i++)
mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
-@@ -2704,21 +2696,18 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2707,21 +2699,18 @@ mt7531_setup(struct dsa_switch *ds)
SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
SYS_CTRL_REG_RST);
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2658,14 +2658,12 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2661,14 +2661,12 @@ mt7531_setup(struct dsa_switch *ds)
val = mt7530_read(priv, MT7531_TOP_SIG_SR);
priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
} else {
mt7530_port_disable(ds, i);
-@@ -2586,9 +2572,7 @@ mt7531_setup_common(struct dsa_switch *d
+@@ -2589,9 +2575,7 @@ mt7531_setup_common(struct dsa_switch *d
mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
if (dsa_is_cpu_port(ds, i)) {
} else {
mt7530_port_disable(ds, i);
-@@ -2681,10 +2665,6 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2684,10 +2668,6 @@ mt7531_setup(struct dsa_switch *ds)
mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
MT7531_GPIO0_INTERRUPT);
/* Disable forwarding by default on all ports */
mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
PCR_MATRIX_CLR);
-@@ -2562,6 +2566,12 @@ mt7531_setup_common(struct dsa_switch *d
+@@ -2565,6 +2569,12 @@ mt7531_setup_common(struct dsa_switch *d
UNU_FFP_MASK);
for (i = 0; i < MT7530_NUM_PORTS; i++) {
err:
if (ret < 0)
dev_err(&bus->dev,
-@@ -2680,16 +2688,19 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2683,16 +2691,19 @@ mt7531_setup(struct dsa_switch *ds)
* phy_[read,write]_mmd_indirect is called, we provide our own
* mt7531_ind_mmd_phy_[read,write] to complete this function.
*/
/* Disable forwarding by default on all ports */
mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
-@@ -2555,8 +2555,8 @@ mt7531_setup_common(struct dsa_switch *d
+@@ -2558,8 +2558,8 @@ mt7531_setup_common(struct dsa_switch *d
/* Clear link settings and enable force mode to force link down
* on all ports until they're enabled later.
*/
/* Disable forwarding by default on all ports */
mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
-@@ -2640,7 +2640,7 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2643,7 +2643,7 @@ mt7531_setup(struct dsa_switch *ds)
/* Force link down on all ports before internal reset */
for (i = 0; i < MT7530_NUM_PORTS; i++)
mt7530_setup_port5(ds, interface);
}
-@@ -2655,9 +2648,6 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2658,9 +2651,6 @@ mt7531_setup(struct dsa_switch *ds)
MT7531_EXT_P_MDIO_12);
}
mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
val = mt7530_read(priv, MT7530_PCR_P(port));
-@@ -2533,7 +2519,7 @@ mt7531_setup_common(struct dsa_switch *d
+@@ -2536,7 +2522,7 @@ mt7531_setup_common(struct dsa_switch *d
mt7530_mib_reset(ds);
/* Disable flooding on all ports */
mt7530_pll_setup(priv);
mt753x_trap_frames(priv);
-@@ -2587,7 +2588,7 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2590,7 +2591,7 @@ mt7531_setup(struct dsa_switch *ds)
}
/* Waiting for MT7530 got to stable */
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2668,7 +2668,9 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2671,7 +2671,9 @@ mt7531_setup(struct dsa_switch *ds)
0);
}
+ if (ret)
+ return ret;
- ds->assisted_learning_on_cpu_port = true;
- ds->mtu_enforcement_ingress = true;
+ return 0;
+ }
@@ -3016,6 +3018,8 @@ mt753x_setup(struct dsa_switch *ds)
ret = mt7530_setup_mdio(priv);
if (ret && priv->irq)
/* Clear link settings and enable force mode to force link down
* on all ports until they're enabled later.
*/
-@@ -2539,7 +2539,7 @@ mt7531_setup_common(struct dsa_switch *d
+@@ -2542,7 +2542,7 @@ mt7531_setup_common(struct dsa_switch *d
mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
UNU_FFP_MASK);
/* Clear link settings and enable force mode to force link down
* on all ports until they're enabled later.
*/
-@@ -2627,7 +2627,7 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2630,7 +2630,7 @@ mt7531_setup(struct dsa_switch *ds)
priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
/* Force link down on all ports before internal reset */
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2636,7 +2636,10 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2639,7 +2639,10 @@ mt7531_setup(struct dsa_switch *ds)
if (!priv->p5_sgmii) {
mt7531_pll_setup(priv);
} else {
.port_setup_message_port = mv88e6xxx_setup_message_port,
.stats_snapshot = mv88e6320_g1_stats_snapshot,
.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
-@@ -5318,6 +5351,7 @@ static const struct mv88e6xxx_ops mv88e6
+@@ -5324,6 +5357,7 @@ static const struct mv88e6xxx_ops mv88e6
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
.port_get_cmode = mv88e6352_port_get_cmode,
--- a/kernel/module/Kconfig
+++ b/kernel/module/Kconfig
-@@ -389,4 +389,11 @@ config MODULES_TREE_LOOKUP
+@@ -390,4 +390,11 @@ config MODULES_TREE_LOOKUP
def_bool y
depends on PERF_EVENTS || TRACING || CFI_CLANG
static void mtk_hw_reset(struct mtk_eth *eth)
{
u32 val;
-@@ -4354,6 +4407,8 @@ static void mtk_pending_work(struct work
+@@ -4370,6 +4423,8 @@ static void mtk_pending_work(struct work
rtnl_lock();
set_bit(MTK_RESETTING, ð->state);
/* Run again reset preliminary configuration in order to avoid any
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -1183,6 +1183,7 @@ struct mtk_reg_map {
+@@ -1191,6 +1191,7 @@ struct mtk_reg_map {
u32 rx_ptr; /* rx base pointer */
u32 rx_cnt_cfg; /* rx max count configuration */
u32 qcrx_ptr; /* rx cpu pointer */
#define QUECTEL_VENDOR_ID 0x2c7c
/* These Quectel products use Quectel's vendor ID */
-@@ -1153,6 +1158,11 @@ static const struct usb_device_id option
+@@ -1154,6 +1159,11 @@ static const struct usb_device_id option
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */
.driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) },
/* Quectel products using Qualcomm vendor ID */
{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)},
{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20),
-@@ -1194,6 +1204,11 @@ static const struct usb_device_id option
+@@ -1195,6 +1205,11 @@ static const struct usb_device_id option
.driver_info = ZLP },
{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
.driver_info = RSVD(4) },
-LINUX_VERSION-6.6 = .88
-LINUX_KERNEL_HASH-6.6.88 = 19df89b63ef7e950de7297dabfac0569183bf87636f4c300a25336c7da490650
+LINUX_VERSION-6.6 = .89
+LINUX_KERNEL_HASH-6.6.89 = c21af7d36068e4ac0704c242eac8459212e6bf4a5d09df941b9b4d17dc1eba00
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -5105,6 +5105,8 @@ static int mtk_probe(struct platform_dev
+@@ -5121,6 +5121,8 @@ static int mtk_probe(struct platform_dev
* for NAPI to work
*/
init_dummy_netdev(ð->dummy_dev);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -1349,6 +1349,22 @@ struct mtk_mac {
+@@ -1357,6 +1357,22 @@ struct mtk_mac {
/* the struct describing the SoC. these are declared in the soc_xyz.c files */
extern const struct of_device_id of_mtk_match[];
static inline bool mtk_is_netsys_v1(struct mtk_eth *eth)
{
return eth->soc->version == 1;
-@@ -1363,6 +1379,7 @@ static inline bool mtk_is_netsys_v3_or_g
+@@ -1371,6 +1387,7 @@ static inline bool mtk_is_netsys_v3_or_g
{
return eth->soc->version > 2;
}
netif_tx_stop_all_queues(dev);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -270,7 +270,7 @@
+@@ -278,7 +278,7 @@
#define MTK_CHK_DDONE_EN BIT(28)
#define MTK_DMAD_WR_WDONE BIT(26)
#define MTK_WCOMP_EN BIT(24)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -271,6 +271,7 @@
+@@ -279,6 +279,7 @@
#define MTK_WCOMP_EN BIT(24)
#define MTK_RESV_BUF (0x80 << 16)
#define MTK_MUTLI_CNT (0x4 << 12)
return 0;
}
-@@ -4647,6 +4794,7 @@ static const struct net_device_ops mtk_n
+@@ -4663,6 +4810,7 @@ static const struct net_device_ops mtk_n
static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
{
const __be32 *_id = of_get_property(np, "reg", NULL);
phy_interface_t phy_mode;
struct phylink *phylink;
struct mtk_mac *mac;
-@@ -4685,16 +4833,41 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4701,16 +4849,41 @@ static int mtk_add_mac(struct mtk_eth *e
mac->id = id;
mac->hw = eth;
mac->of_node = np;
}
memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
-@@ -4777,8 +4950,21 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4793,8 +4966,21 @@ static int mtk_add_mac(struct mtk_eth *e
phy_interface_zero(mac->phylink_config.supported_interfaces);
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
mac->phylink_config.supported_interfaces);
phylink = phylink_create(&mac->phylink_config,
of_fwnode_handle(mac->of_node),
phy_mode, &mtk_phylink_ops);
-@@ -4829,6 +5015,26 @@ free_netdev:
+@@ -4845,6 +5031,26 @@ free_netdev:
return err;
}
void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
{
struct net_device *dev, *tmp;
-@@ -4975,7 +5181,8 @@ static int mtk_probe(struct platform_dev
+@@ -4991,7 +5197,8 @@ static int mtk_probe(struct platform_dev
regmap_write(cci, 0, 3);
}
err = mtk_sgmii_init(eth);
if (err)
-@@ -5086,6 +5293,24 @@ static int mtk_probe(struct platform_dev
+@@ -5102,6 +5309,24 @@ static int mtk_probe(struct platform_dev
}
}
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
err = devm_request_irq(eth->dev, eth->irq[0],
mtk_handle_irq, 0,
-@@ -5189,6 +5414,11 @@ static int mtk_remove(struct platform_de
+@@ -5205,6 +5430,11 @@ static int mtk_remove(struct platform_de
mtk_stop(eth->netdev[i]);
mac = netdev_priv(eth->netdev[i]);
phylink_disconnect_phy(mac->phylink);
#include <linux/rhashtable.h>
#include <linux/dim.h>
#include <linux/bitfield.h>
-@@ -516,6 +517,21 @@
+@@ -524,6 +525,21 @@
#define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
#define INTF_MODE_RGMII_10_100 0
/* GPIO port control registers for GMAC 2*/
#define GPIO_OD33_CTRL8 0x4c0
#define GPIO_BIAS_CTRL 0xed0
-@@ -541,6 +557,7 @@
+@@ -549,6 +565,7 @@
#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
#define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
#define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
/* ethernet subsystem clock register */
-@@ -579,6 +596,11 @@
+@@ -587,6 +604,11 @@
#define GEPHY_MAC_SEL BIT(1)
/* Top misc registers */
#define USB_PHY_SWITCH_REG 0x218
#define QPHY_SEL_MASK GENMASK(1, 0)
#define SGMII_QPHY_SEL 0x2
-@@ -603,6 +625,8 @@
+@@ -611,6 +633,8 @@
#define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
#define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)
#define MTK_FE_CDM1_FSM 0x220
#define MTK_FE_CDM2_FSM 0x224
#define MTK_FE_CDM3_FSM 0x238
-@@ -611,6 +635,11 @@
+@@ -619,6 +643,11 @@
#define MTK_FE_CDM6_FSM 0x328
#define MTK_FE_GDM1_FSM 0x228
#define MTK_FE_GDM2_FSM 0x22C
#define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))
-@@ -735,12 +764,8 @@ enum mtk_clks_map {
+@@ -743,12 +772,8 @@ enum mtk_clks_map {
MTK_CLK_ETHWARP_WOCPU2,
MTK_CLK_ETHWARP_WOCPU1,
MTK_CLK_ETHWARP_WOCPU0,
MTK_CLK_TOP_ETH_GMII_SEL,
MTK_CLK_TOP_ETH_REFCK_50M_SEL,
MTK_CLK_TOP_ETH_SYS_200M_SEL,
-@@ -811,19 +836,9 @@ enum mtk_clks_map {
+@@ -819,19 +844,9 @@ enum mtk_clks_map {
BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
BIT_ULL(MTK_CLK_CRYPTO) | \
BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
-@@ -957,6 +972,8 @@ enum mkt_eth_capabilities {
+@@ -965,6 +980,8 @@ enum mkt_eth_capabilities {
MTK_RGMII_BIT = 0,
MTK_TRGMII_BIT,
MTK_SGMII_BIT,
MTK_ESW_BIT,
MTK_GEPHY_BIT,
MTK_MUX_BIT,
-@@ -977,8 +994,11 @@ enum mkt_eth_capabilities {
+@@ -985,8 +1002,11 @@ enum mkt_eth_capabilities {
MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
/* PATH BITS */
MTK_ETH_PATH_GMAC1_RGMII_BIT,
-@@ -986,14 +1006,21 @@ enum mkt_eth_capabilities {
+@@ -994,14 +1014,21 @@ enum mkt_eth_capabilities {
MTK_ETH_PATH_GMAC1_SGMII_BIT,
MTK_ETH_PATH_GMAC2_RGMII_BIT,
MTK_ETH_PATH_GMAC2_SGMII_BIT,
#define MTK_ESW BIT_ULL(MTK_ESW_BIT)
#define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
#define MTK_MUX BIT_ULL(MTK_MUX_BIT)
-@@ -1016,10 +1043,16 @@ enum mkt_eth_capabilities {
+@@ -1024,10 +1051,16 @@ enum mkt_eth_capabilities {
BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
/* Supported path present on SoCs */
#define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
-@@ -1027,8 +1060,13 @@ enum mkt_eth_capabilities {
+@@ -1035,8 +1068,13 @@ enum mkt_eth_capabilities {
#define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
#define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
#define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
#define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
-@@ -1036,7 +1074,12 @@ enum mkt_eth_capabilities {
+@@ -1044,7 +1082,12 @@ enum mkt_eth_capabilities {
#define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
/* MUXes present on SoCs */
/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
-@@ -1055,10 +1098,20 @@ enum mkt_eth_capabilities {
+@@ -1063,10 +1106,20 @@ enum mkt_eth_capabilities {
(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
MTK_SHARED_SGMII)
#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
-@@ -1090,8 +1143,12 @@ enum mkt_eth_capabilities {
+@@ -1098,8 +1151,12 @@ enum mkt_eth_capabilities {
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
MTK_RSTCTRL_PPE1 | MTK_SRAM)
struct mtk_tx_dma_desc_info {
dma_addr_t addr;
-@@ -1338,6 +1395,9 @@ struct mtk_mac {
+@@ -1346,6 +1403,9 @@ struct mtk_mac {
struct device_node *of_node;
struct phylink *phylink;
struct phylink_config phylink_config;
struct mtk_eth *hw;
struct mtk_hw_stats *hw_stats;
__be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
-@@ -1461,6 +1521,19 @@ static inline u32 mtk_get_ib2_multicast_
+@@ -1469,6 +1529,19 @@ static inline u32 mtk_get_ib2_multicast_
return MTK_FOE_IB2_MULTICAST;
}
/* read the hardware status register */
void mtk_stats_update_mac(struct mtk_mac *mac);
-@@ -1469,8 +1542,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
+@@ -1477,8 +1550,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -5450,7 +5450,7 @@ static const struct mtk_soc_data mt2701_
+@@ -5466,7 +5466,7 @@ static const struct mtk_soc_data mt2701_
.desc_size = sizeof(struct mtk_rx_dma),
.irq_done_mask = MTK_RX_DONE_INT,
.dma_l4_valid = RX_DMA_L4_VALID,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5478,7 +5478,7 @@ static const struct mtk_soc_data mt7621_
+@@ -5494,7 +5494,7 @@ static const struct mtk_soc_data mt7621_
.desc_size = sizeof(struct mtk_rx_dma),
.irq_done_mask = MTK_RX_DONE_INT,
.dma_l4_valid = RX_DMA_L4_VALID,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5508,7 +5508,7 @@ static const struct mtk_soc_data mt7622_
+@@ -5524,7 +5524,7 @@ static const struct mtk_soc_data mt7622_
.desc_size = sizeof(struct mtk_rx_dma),
.irq_done_mask = MTK_RX_DONE_INT,
.dma_l4_valid = RX_DMA_L4_VALID,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5537,7 +5537,7 @@ static const struct mtk_soc_data mt7623_
+@@ -5553,7 +5553,7 @@ static const struct mtk_soc_data mt7623_
.desc_size = sizeof(struct mtk_rx_dma),
.irq_done_mask = MTK_RX_DONE_INT,
.dma_l4_valid = RX_DMA_L4_VALID,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5563,7 +5563,7 @@ static const struct mtk_soc_data mt7629_
+@@ -5579,7 +5579,7 @@ static const struct mtk_soc_data mt7629_
.desc_size = sizeof(struct mtk_rx_dma),
.irq_done_mask = MTK_RX_DONE_INT,
.dma_l4_valid = RX_DMA_L4_VALID,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5595,7 +5595,7 @@ static const struct mtk_soc_data mt7981_
+@@ -5611,7 +5611,7 @@ static const struct mtk_soc_data mt7981_
.dma_l4_valid = RX_DMA_L4_VALID_V2,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
};
-@@ -5625,7 +5625,7 @@ static const struct mtk_soc_data mt7986_
+@@ -5641,7 +5641,7 @@ static const struct mtk_soc_data mt7986_
.dma_l4_valid = RX_DMA_L4_VALID_V2,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
};
-@@ -5678,7 +5678,7 @@ static const struct mtk_soc_data rt5350_
+@@ -5694,7 +5694,7 @@ static const struct mtk_soc_data rt5350_
.dma_l4_valid = RX_DMA_L4_VALID_PDMA,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
help
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4562,6 +4562,7 @@ static int mtk_get_sset_count(struct net
+@@ -4578,6 +4578,7 @@ static int mtk_get_sset_count(struct net
static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data)
{
struct page_pool_stats stats = {};
int i;
-@@ -4574,6 +4575,7 @@ static void mtk_ethtool_pp_stats(struct
+@@ -4590,6 +4591,7 @@ static void mtk_ethtool_pp_stats(struct
page_pool_get_stats(ring->page_pool, &stats);
}
page_pool_ethtool_stats_get(data, &stats);
wcss->mem_phys, wcss->mem_size,
NULL);
}
-@@ -777,6 +801,12 @@ static int q6_wcss_remove(struct platfor
- return 0;
+@@ -775,6 +799,12 @@ static void q6_wcss_remove(struct platfo
+ rproc_free(rproc);
}
+static const struct wcss_data q6_ipq5018_res_init = {
static const struct wcss_data q6_ipq5332_res_init = {
.pasid = MPD_WCNSS_PAS_ID,
.share_upd_info_to_q6 = true,
-@@ -787,6 +817,7 @@ static const struct wcss_data q6_ipq9574
+@@ -785,6 +815,7 @@ static const struct wcss_data q6_ipq9574
};
static const struct of_device_id q6_wcss_of_match[] = {
}
}
-@@ -803,13 +850,15 @@ static int q6_wcss_remove(struct platfor
+@@ -801,13 +848,15 @@ static void q6_wcss_remove(struct platfo
static const struct wcss_data q6_ipq5018_res_init = {
.pasid = MPD_WCNSS_PAS_ID,
}
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
-@@ -3708,7 +3708,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3711,7 +3711,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
full_len = urb->transfer_buffer_length;
/* If we have scatter/gather list, we use it. */
projects / thirdparty / openwrt.git / commitdiff
