]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: rockchip: Move rk3568 PCIe3 MSI to use GIC ITS
authorChukun Pan <amadeus@jmu.edu.cn>
Sat, 8 Mar 2025 09:30:08 +0000 (17:30 +0800)
committerHeiko Stuebner <heiko@sntech.de>
Thu, 8 May 2025 17:48:50 +0000 (19:48 +0200)
Following commit b956c9de9175 ("arm64: dts: rockchip: rk356x: Move
PCIe MSI to use GIC ITS instead of MBI"), change the PCIe3 controller's
MSI on rk3568 to use ITS, so that all MSI-X can work properly.

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250308093008.568437-2-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm64/boot/dts/rockchip/rk3568.dtsi

index 695cccbdab0f98e8af830d5849e2012a9da6a7dc..e719a3df126c59ce532d3e26cf358fd2160c1d9c 100644 (file)
                compatible = "rockchip,rk3568-pcie";
                #address-cells = <3>;
                #size-cells = <2>;
-               bus-range = <0x0 0xf>;
+               bus-range = <0x10 0x1f>;
                clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
                         <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
                         <&cru CLK_PCIE30X1_AUX_NDFT>;
                num-ib-windows = <6>;
                num-ob-windows = <2>;
                max-link-speed = <3>;
-               msi-map = <0x0 &gic 0x1000 0x1000>;
+               msi-map = <0x1000 &its 0x1000 0x1000>;
                num-lanes = <1>;
                phys = <&pcie30phy>;
                phy-names = "pcie-phy";
                compatible = "rockchip,rk3568-pcie";
                #address-cells = <3>;
                #size-cells = <2>;
-               bus-range = <0x0 0xf>;
+               bus-range = <0x20 0x2f>;
                clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
                         <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
                         <&cru CLK_PCIE30X2_AUX_NDFT>;
                num-ib-windows = <6>;
                num-ob-windows = <2>;
                max-link-speed = <3>;
-               msi-map = <0x0 &gic 0x2000 0x1000>;
+               msi-map = <0x2000 &its 0x2000 0x1000>;
                num-lanes = <2>;
                phys = <&pcie30phy>;
                phy-names = "pcie-phy";