drm/amd/display: pg cntl update based on previous asic.

[why]
switch to well tested sequence.

Reviewed-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c
index 3685080ce9dc4d7781a97e079bd3dfc5438990bd..96290538a889d4a16c161b99380ee7cf3b6772cc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c
@@ -176,11 +176,12 @@ void pg_cntl42_hubp_dpp_pg_control(struct pg_cntl *pg_cntl, unsigned int hubp_dp
        uint32_t pwr_status = power_on ? 0 : 2;
        uint32_t org_ip_request_cntl;
        bool block_enabled;
+       bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg ||
+                      pg_cntl->ctx->dc->debug.disable_hubp_power_gate ||
+                      pg_cntl->ctx->dc->debug.disable_dpp_power_gate ||
+                      pg_cntl->ctx->dc->idle_optimizations_allowed;
 
-       if (pg_cntl->ctx->dc->debug.ignore_pg ||
-               pg_cntl->ctx->dc->debug.disable_hubp_power_gate ||
-               pg_cntl->ctx->dc->debug.disable_dpp_power_gate ||
-               pg_cntl->ctx->dc->idle_optimizations_allowed)
+       if (skip_pg && !power_on)
                return;
 
        block_enabled = pg_cntl42_hubp_dpp_pg_status(pg_cntl, hubp_dpp_inst);