soc: rockchip: grf: Set pwm2/xin32k pad default to xin32k for rk3368

PWM2 and xin32k share the same pad, but some peripheral need the xin32k
clock to run properly, such as tsadc. I have observed that this pad is
used as xin32k by default on some existing board [1], so it maybe more
appropriate to set it to xin32k by default.

I also tested it on another rk3368 based board [2], without this adjust,
tsadc does not work properly.

[1] https://rockchip.fr/geekbox/Geekbox_V1.23.pdf
[2] https://ieiao.github.io/wiki/embedded-dev/rockchip/rk3368

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
Link: https://patch.msgid.link/20250906142125.7602-1-cn.liweihao@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c
index 344870da7675fcde38ef1d7d9dcf243fcb9711e4..c0c2ec1296f55c36930a7c508b40c7c1dc49c9a0 100644 (file)
--- a/drivers/soc/rockchip/grf.c
+++ b/drivers/soc/rockchip/grf.c
@@ -98,6 +98,17 @@ static const struct rockchip_grf_info rk3368_grf __initconst = {
        .num_values = ARRAY_SIZE(rk3368_defaults),
 };
 
+#define RK3368_PMUGRF_SOC_CON0         0x100
+
+static const struct rockchip_grf_value rk3368_pmugrf_defaults[] __initconst = {
+       { "pwm2 select", RK3368_PMUGRF_SOC_CON0, FIELD_PREP_WM16_CONST(BIT(7), 0) },
+};
+
+static const struct rockchip_grf_info rk3368_pmugrf __initconst = {
+       .values = rk3368_pmugrf_defaults,
+       .num_values = ARRAY_SIZE(rk3368_pmugrf_defaults),
+};
+
 #define RK3399_GRF_SOC_CON7            0xe21c
 
 static const struct rockchip_grf_value rk3399_defaults[] __initconst = {
@@ -175,6 +186,9 @@ static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
        }, {
                .compatible = "rockchip,rk3368-grf",
                .data = (void *)&rk3368_grf,
+       }, {
+               .compatible = "rockchip,rk3368-pmugrf",
+               .data = (void *)&rk3368_pmugrf,
        }, {
                .compatible = "rockchip,rk3399-grf",
                .data = (void *)&rk3399_grf,