VREV32Q_M_F
])
+(define_int_iterator MVE_FP_M_N_VDUPQ_ONLY [
+ VDUPQ_M_N_F
+ ])
+
+(define_int_iterator MVE_FP_N_VDUPQ_ONLY [
+ VDUPQ_N_F
+ ])
+
;; MVE integer binary operations.
(define_code_iterator MVE_INT_BINARY_RTX [plus minus mult])
(VCLSQ_S "vcls")
(VCLZQ_M_S "vclz") (VCLZQ_M_U "vclz")
(VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate") (VCREATEQ_F "vcreate")
+ (VDUPQ_M_N_S "vdup") (VDUPQ_M_N_U "vdup") (VDUPQ_M_N_F "vdup")
+ (VDUPQ_N_S "vdup") (VDUPQ_N_U "vdup") (VDUPQ_N_F "vdup")
(VEORQ_M_S "veor") (VEORQ_M_U "veor") (VEORQ_M_F "veor")
(VHADDQ_M_N_S "vhadd") (VHADDQ_M_N_U "vhadd")
(VHADDQ_M_S "vhadd") (VHADDQ_M_U "vhadd")
;;
;; [vdupq_n_f])
;;
-(define_insn "mve_vdupq_n_f<mode>"
+(define_insn "@mve_<mve_insn>q_n_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
- VDUPQ_N_F))
+ MVE_FP_N_VDUPQ_ONLY))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vdup.%#<V_sz_elem>\t%q0, %1"
+ "<mve_insn>.%#<V_sz_elem>\t%q0, %1"
[(set_attr "type" "mve_move")
])
;;
;; [vdupq_n_u, vdupq_n_s])
;;
-(define_insn "mve_vdupq_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
VDUPQ_N))
]
"TARGET_HAVE_MVE"
- "vdup.%#<V_sz_elem>\t%q0, %1"
+ "<mve_insn>.%#<V_sz_elem>\t%q0, %1"
[(set_attr "type" "mve_move")
])
;;
;; [vdupq_m_n_s, vdupq_m_n_u])
;;
-(define_insn "mve_vdupq_m_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
VDUPQ_M_N))
]
"TARGET_HAVE_MVE"
- "vpst\;vdupt.%#<V_sz_elem>\t%q0, %2"
+ "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
;;
;; [vdupq_m_n_f])
;;
-(define_insn "mve_vdupq_m_n_f<mode>"
+(define_insn "@mve_<mve_insn>q_m_n_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
(match_operand:<V_elem> 2 "s_register_operand" "r")
(match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
- VDUPQ_M_N_F))
+ MVE_FP_M_N_VDUPQ_ONLY))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vdupt.%#<V_sz_elem>\t%q0, %2"
+ "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])