clk: imx: pll14xx: Use unsigned format specifier

The debug outputs use %d for clock rates resulting in negative clock rate
during rate calculation.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Link: https://patch.msgid.link/20260317121953.1100619-1-alexander.stein@ew.tq-group.com
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index 7552aaafc3395e8ce463f94716c6f9e605115035..39600ee22be3066683b562aa6f2a8b750d19c4cc 100644 (file)
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -151,7 +151,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat
        /* First try if we can get the desired rate from one of the static entries */
        tt = imx_get_pll_settings(pll, rate);
        if (tt) {
-               pr_debug("%s: in=%ld, want=%ld, Using PLL setting from table\n",
+               pr_debug("%s: in=%lu, want=%lu, Using PLL setting from table\n",
                         clk_hw_get_name(&pll->hw), prate, rate);
                t->rate = tt->rate;
                t->mdiv = tt->mdiv;
@@ -173,7 +173,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat
 
        if (rate >= rate_min && rate <= rate_max) {
                kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate);
-               pr_debug("%s: in=%ld, want=%ld Only adjust kdiv %ld -> %d\n",
+               pr_debug("%s: in=%lu, want=%lu Only adjust kdiv %ld -> %d\n",
                         clk_hw_get_name(&pll->hw), prate, rate,
                         FIELD_GET(KDIV_MASK, pll_div_ctl1), kdiv);
                fout = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);
@@ -211,7 +211,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat
                }
        }
 found:
-       pr_debug("%s: in=%ld, want=%ld got=%d (pdiv=%d sdiv=%d mdiv=%d kdiv=%d)\n",
+       pr_debug("%s: in=%lu, want=%lu got=%u (pdiv=%d sdiv=%d mdiv=%d kdiv=%d)\n",
                 clk_hw_get_name(&pll->hw), prate, rate, t->rate, t->pdiv, t->sdiv,
                 t->mdiv, t->kdiv);
 }