PLATFORM_CASE(ALDERLAKE_P, A0),
PLATFORM_CASE(ALDERLAKE_P, B0),
PLATFORM_CASE(ALDERLAKE_P, C0),
+ SUBPLATFORM_CASE(ALDERLAKE_S, RPLS, D0),
SUBPLATFORM_CASE(DG2, G10, A0),
SUBPLATFORM_CASE(DG2, G10, A1),
SUBPLATFORM_CASE(DG2, G10, B0),
.require_force_probe = true,
};
+static const u16 adls_rpls_ids[] = { XE_RPLS_IDS(NOP), 0 };
+
static const struct xe_device_desc adl_s_desc = {
.graphics = &graphics_xelp,
.media = &media_xem,
PLATFORM(XE_ALDERLAKE_S),
.has_llc = 1,
.require_force_probe = true,
+ .subplatforms = (const struct xe_subplatform_desc[]) {
+ { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
+ {},
+ },
};
static const u16 adlp_rplu_ids[] = { XE_RPLU_IDS(NOP), 0 };
XE_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
XE_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc),
XE_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
+ XE_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
XE_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc),
XE_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc),
XE_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc),