]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/xe/rpls: Add RPLS Support
authorAnusha Srivatsa <anusha.srivatsa@intel.com>
Thu, 5 Oct 2023 20:54:48 +0000 (13:54 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 21 Dec 2023 16:42:58 +0000 (11:42 -0500)
Add RPLS support that was missing apart from the PCI IDs.

v2: Also add the support in xe_wa_test kunit
v3: rebased.

Cc: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>(v1)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231005205450.3177354-4-anusha.srivatsa@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/xe/tests/xe_wa_test.c
drivers/gpu/drm/xe/xe_pci.c
drivers/gpu/drm/xe/xe_platform_types.h

index 16f7f157c8753ce1f35d460d5ccd635dbfabdea6..69c9ea1fa82bcf1fc7e917e38b70e0e4ed04b687 100644 (file)
@@ -49,6 +49,7 @@ static const struct platform_test_case cases[] = {
        PLATFORM_CASE(ALDERLAKE_P, A0),
        PLATFORM_CASE(ALDERLAKE_P, B0),
        PLATFORM_CASE(ALDERLAKE_P, C0),
+       SUBPLATFORM_CASE(ALDERLAKE_S, RPLS, D0),
        SUBPLATFORM_CASE(DG2, G10, A0),
        SUBPLATFORM_CASE(DG2, G10, A1),
        SUBPLATFORM_CASE(DG2, G10, B0),
index 2652e7426258ac1b7b97d2a00042d48b8a3bd7a2..0efe01885cf8beb60d4a2166a0b01e51f3f1064a 100644 (file)
@@ -213,12 +213,18 @@ static const struct xe_device_desc rkl_desc = {
        .require_force_probe = true,
 };
 
+static const u16 adls_rpls_ids[] = { XE_RPLS_IDS(NOP), 0 };
+
 static const struct xe_device_desc adl_s_desc = {
        .graphics = &graphics_xelp,
        .media = &media_xem,
        PLATFORM(XE_ALDERLAKE_S),
        .has_llc = 1,
        .require_force_probe = true,
+       .subplatforms = (const struct xe_subplatform_desc[]) {
+               { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
+               {},
+       },
 };
 
 static const u16 adlp_rplu_ids[] = { XE_RPLU_IDS(NOP), 0 };
@@ -335,6 +341,7 @@ static const struct pci_device_id pciidlist[] = {
        XE_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
        XE_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc),
        XE_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
+       XE_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
        XE_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc),
        XE_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc),
        XE_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc),
index b6fe4342f9f6a7fdba93b6074647d548826dff78..553f53dbd093e38d3f5df7c40fc74e1ec49fd886 100644 (file)
@@ -28,6 +28,7 @@ enum xe_subplatform {
        XE_SUBPLATFORM_UNINITIALIZED = 0,
        XE_SUBPLATFORM_NONE,
        XE_SUBPLATFORM_ALDERLAKE_P_RPLU,
+       XE_SUBPLATFORM_ALDERLAKE_S_RPLS,
        XE_SUBPLATFORM_DG2_G10,
        XE_SUBPLATFORM_DG2_G11,
        XE_SUBPLATFORM_DG2_G12,