Fix syntax error in ARM offset addressing. Spotted by Jukka Ukkonen.

diff --git a/ChangeLog b/ChangeLog
index a2844e92606463ae8c04a1d81ef3f8d2e52eaa22..bb86bf0da47d497d533b3b5cda8aea91379bdcd1 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,7 @@
 2015-04-29  Niels Möller  <nisse@lysator.liu.se>
 
+       * arm/v6/sha256-compress.asm: Fix syntax error in offset
+       addressing. Spotted by Jukka Ukkonen.
        * arm/v6/aes-decrypt-internal.asm: Drop %-prefix on r12 register.
        * arm/v6/aes-encrypt-internal.asm: Likewise.
 

diff --git a/arm/v6/sha256-compress.asm b/arm/v6/sha256-compress.asm
index 75607789dd11d2694922ca5ab1d555cc33c7b6b3..e6f4e1e932d29fe8565d1245790e84e437a81299 100644 (file)
--- a/arm/v6/sha256-compress.asm
+++ b/arm/v6/sha256-compress.asm
@@ -126,7 +126,7 @@ define(<NOEXPN>, <
 PROLOGUE(_nettle_sha256_compress)
        push    {r4,r5,r6,r7,r8,r10,r11,r14}
        sub     sp, sp, #68
-       str     STATE, [sp, +#64]
+       str     STATE, [sp, #+64]
 
        C Load data up front, since we don't have enough registers
        C to load and shift on-the-fly
@@ -199,7 +199,7 @@ PROLOGUE(_nettle_sha256_compress)
        EXPN(15) ROUND(SB,SC,SD,SE,SF,SG,SH,SA)
        bne     .Loop2
 
-       ldr     STATE, [sp, +#64]
+       ldr     STATE, [sp, #+64]
        C No longer needed registers
        ldm     STATE, {r1,r2,r12,r14}
        add     SA, SA, r1