clk: qcom: smd-rpm: Add clocks for SDM429

SDM429 has mostly the same rpm clocks as MSM8953, but lacks RF_CLK3 and
IPA_CLK and additionally has the BB_CLK3.

Signed-off-by: Daniil Titov <daniilt971@gmail.com>
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Link: https://lore.kernel.org/r/20250212-sdm429-rpm-v1-2-0a24ac19a478@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index 29ef08a9d50b47fb71ac253c6f50f4c28f4d6519..3fbaa646286f284da12b902873b079863a2c0d77 100644 (file)
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -486,6 +486,7 @@ DEFINE_CLK_SMD_RPM(qup, QCOM_SMD_RPM_QUP_CLK, 0);
 
 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk1, 1, 19200000);
 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk2, 2, 19200000);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk3, 3, 19200000);
 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk1, 1, 19200000);
 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk2, 2, 19200000);
 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk3, 3, 19200000);
@@ -1046,6 +1047,36 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
        .num_icc_clks = ARRAY_SIZE(msm8998_icc_clks),
 };
 
+static struct clk_smd_rpm *sdm429_clks[] = {
+       [RPM_SMD_XO_CLK_SRC]            = &clk_smd_rpm_branch_bi_tcxo,
+       [RPM_SMD_XO_A_CLK_SRC]          = &clk_smd_rpm_branch_bi_tcxo_a,
+       [RPM_SMD_QDSS_CLK]              = &clk_smd_rpm_qdss_clk,
+       [RPM_SMD_QDSS_A_CLK]            = &clk_smd_rpm_qdss_a_clk,
+       [RPM_SMD_BB_CLK1]               = &clk_smd_rpm_bb_clk1,
+       [RPM_SMD_BB_CLK1_A]             = &clk_smd_rpm_bb_clk1_a,
+       [RPM_SMD_BB_CLK2]               = &clk_smd_rpm_bb_clk2,
+       [RPM_SMD_BB_CLK2_A]             = &clk_smd_rpm_bb_clk2_a,
+       [RPM_SMD_BB_CLK3]               = &clk_smd_rpm_bb_clk3,
+       [RPM_SMD_BB_CLK3_A]             = &clk_smd_rpm_bb_clk3_a,
+       [RPM_SMD_RF_CLK2]               = &clk_smd_rpm_rf_clk2,
+       [RPM_SMD_RF_CLK2_A]             = &clk_smd_rpm_rf_clk2_a,
+       [RPM_SMD_DIV_CLK2]              = &clk_smd_rpm_div_clk2,
+       [RPM_SMD_DIV_A_CLK2]            = &clk_smd_rpm_div_clk2_a,
+       [RPM_SMD_BB_CLK1_PIN]           = &clk_smd_rpm_bb_clk1_pin,
+       [RPM_SMD_BB_CLK1_A_PIN]         = &clk_smd_rpm_bb_clk1_a_pin,
+       [RPM_SMD_BB_CLK2_PIN]           = &clk_smd_rpm_bb_clk2_pin,
+       [RPM_SMD_BB_CLK2_A_PIN]         = &clk_smd_rpm_bb_clk2_a_pin,
+       [RPM_SMD_BB_CLK3_PIN]           = &clk_smd_rpm_bb_clk3_pin,
+       [RPM_SMD_BB_CLK3_A_PIN]         = &clk_smd_rpm_bb_clk3_a_pin,
+};
+
+static const struct rpm_smd_clk_desc rpm_clk_sdm429 = {
+       .clks = sdm429_clks,
+       .num_clks = ARRAY_SIZE(sdm429_clks),
+       .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
+       .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
+};
+
 static struct clk_smd_rpm *sdm660_clks[] = {
        [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
        [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
@@ -1276,6 +1307,7 @@ static const struct of_device_id rpm_smd_clk_match_table[] = {
        { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
        { .compatible = "qcom,rpmcc-qcm2290", .data = &rpm_clk_qcm2290 },
        { .compatible = "qcom,rpmcc-qcs404",  .data = &rpm_clk_qcs404  },
+       { .compatible = "qcom,rpmcc-sdm429",  .data = &rpm_clk_sdm429  },
        { .compatible = "qcom,rpmcc-sdm660",  .data = &rpm_clk_sdm660  },
        { .compatible = "qcom,rpmcc-sm6115",  .data = &rpm_clk_sm6115  },
        { .compatible = "qcom,rpmcc-sm6125",  .data = &rpm_clk_sm6125  },