mips: add a special case for beq r0, r0, imm

This results in unconditional PUTs to PC in generated IR code.

This fixes:

    memcheck/tests/cdebug_zlib
    memcheck/tests/cdebug_zlib_gnu
    memcheck/tests/origin2-not-quite
    memcheck/tests/origin5-bz2
    none/tests/mips64/branch_and_jump_instructions

diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c
index d915487af0aff126c00cab9bf709d1dbc4a6f1b1..489d91afb7c6d6f17df58d09582c85432eea7781 100644 (file)
--- a/VEX/priv/guest_mips_toIR.c
+++ b/VEX/priv/guest_mips_toIR.c
@@ -20034,16 +20034,31 @@ static UInt disInstr_MIPS_WRK_00(UInt cins, const VexArchInfo* archinfo,
          *lastn = mkexpr(t0);
          break;
 
-      case 0x04:  /* BEQ */
-         DIP("beq r%u, r%u, %u", rs, rt, imm);
+      case 0x04:  /* BEQ, B */
+         if (rs == 0 && rt == 0) {
+            ULong branch_offset;
+            t0 = newTemp(ty);
+            DIP("b %u", imm);
 
-         if (mode64)
-            dis_branch(False, binop(Iop_CmpEQ64, getIReg(rs), getIReg(rt)),
-                       imm, bstmt);
-         else
-            dis_branch(False, binop(Iop_CmpEQ32, getIReg(rs), getIReg(rt)),
-                       imm, bstmt);
+            if (mode64) {
+               branch_offset = extend_s_18to64(imm << 2);
+               assign(t0, mkU64(guest_PC_curr_instr + 4 + branch_offset));
+            } else {
+               branch_offset = extend_s_18to32(imm << 2);
+               assign(t0, mkU32(guest_PC_curr_instr + 4 + branch_offset));
+            }
 
+            *lastn = mkexpr(t0);
+         } else {
+            DIP("beq r%u, r%u, %u", rs, rt, imm);
+
+            if (mode64)
+               dis_branch(False, binop(Iop_CmpEQ64, getIReg(rs), getIReg(rt)),
+                          imm, bstmt);
+            else
+               dis_branch(False, binop(Iop_CmpEQ32, getIReg(rs), getIReg(rt)),
+                          imm, bstmt);
+         }
          break;
 
       case 0x05:  /* BNE */