]> git.ipfire.org Git - thirdparty/openwrt.git/commitdiff
realtek: pcs: fix PLL_CML_CTRL for serdes 0/1
authorMarkus Stockhausen <markus.stockhausen@gmx.de>
Mon, 9 Feb 2026 19:26:07 +0000 (20:26 +0100)
committerRobert Marko <robimarko@gmail.com>
Thu, 12 Feb 2026 15:58:46 +0000 (16:58 +0100)
Setup of register PLL_CML_CTRL has two issues.

- It clears out bits 4-31 due to a wrong mask
- Setup of bits 0-3 is not generic but depends on the mode of
  serdes 0/1

Fix that by relocating the code and adapting the mask. The error
exists for longer but it has survived the pcs refactoring. Thus
blame the corresponding refactoring commit.

Fixes: b670d48 ("realtek: pcs: rtl838x: refactor imported code")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21956
Signed-off-by: Robert Marko <robimarko@gmail.com>
target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c

index 47980913f326771e155511fa2e7399193bea39e4..33fc8b218f3a79205691cf72e5bc80a426508ad1 100644 (file)
@@ -492,6 +492,9 @@ static void rtpcs_generic_sds_restart_autoneg(struct rtpcs_serdes *sds)
 
 static void rtpcs_838x_sds_patch_01_qsgmii_6275b(struct rtpcs_ctrl *ctrl)
 {
+       /* CKREFBUF_S0S1 for QSGMII */
+       regmap_write_bits(ctrl->map, RTPCS_838X_PLL_CML_CTRL, 0xf, 0xf);
+
        rtpcs_sds_write(SDS(ctrl, 0), 1, 3, 0xf46f);
        rtpcs_sds_write(SDS(ctrl, 0), 1, 2, 0x85fa);
        rtpcs_sds_write(SDS(ctrl, 1), 1, 2, 0x85fa);
@@ -729,18 +732,11 @@ static int rtpcs_838x_sds_patch(struct rtpcs_serdes *sds,
 
 static int rtpcs_838x_init_serdes_common(struct rtpcs_ctrl *ctrl)
 {
-       u32 val;
-
        dev_dbg(ctrl->dev, "Init RTL838X SerDes common\n");
 
        /* enable R/W of some protected registers */
        regmap_write(ctrl->map, RTPCS_838X_INT_RW_CTRL, 0x3);
 
-       regmap_read(ctrl->map, RTPCS_838X_PLL_CML_CTRL, &val);
-       dev_dbg(ctrl->dev, "PLL control register: %x\n", val);
-       regmap_write_bits(ctrl->map, RTPCS_838X_PLL_CML_CTRL, 0xfffffff0,
-                         0xaaaaaaaf & 0xf);
-
        /* power off and reset all SerDes */
        regmap_write(ctrl->map, RTPCS_838X_SDS_CFG_REG, 0x3f);
        regmap_write(ctrl->map, RTPCS_838X_RST_GLB_CTRL_0, 0x10); /* SW_SERDES_RST */