]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/amdgpu: add soc config init for GC v12_1
authorLikun Gao <Likun.Gao@amd.com>
Fri, 21 Mar 2025 03:23:44 +0000 (11:23 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 8 Dec 2025 19:13:37 +0000 (14:13 -0500)
Add function to initialize soc configuration information
for GC 12.1.0 ASICs.
Use it to map IPs and other SOC related information once IP
configuration information is available through discovery.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
drivers/gpu/drm/amd/amdgpu/soc_v1_0.h

index ffffc60c98db5d1b1634ddd94f2ecfc512088328..20d05a3e4516e80e1cfab65d27300561400a5d59 100644 (file)
@@ -2592,6 +2592,9 @@ static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev)
        case IP_VERSION(9, 5, 0):
                aqua_vanjaram_init_soc_config(adev);
                break;
+       case IP_VERSION(12, 1, 0):
+               soc_v1_0_init_soc_config(adev);
+               break;
        default:
                break;
        }
index 815f130f760c77283aaecea31b6bef9a5f9f0d9f..0ede5e22e905f3372bdbd742a4dc506c9e1af64b 100644 (file)
@@ -24,6 +24,7 @@
 #include "soc15.h"
 #include "soc15_common.h"
 #include "soc_v1_0.h"
+#include "amdgpu_ip.h"
 
 #include "gc/gc_12_1_0_offset.h"
 #include "gc/gc_12_1_0_sh_mask.h"
@@ -334,3 +335,12 @@ const struct amdgpu_ip_block_version soc_v1_0_common_ip_block = {
        .rev = 0,
        .funcs = &soc_v1_0_common_ip_funcs,
 };
+
+int soc_v1_0_init_soc_config(struct amdgpu_device *adev)
+{
+       adev->sdma.num_inst_per_xcc = 2;
+
+       amdgpu_ip_map_init(adev);
+
+       return 0;
+}
index d9de040c37291c1ce567b9bddb75f38764e88fff..23517c3a3d1bc2d13a4000879cdce1e525331c0a 100644 (file)
@@ -29,5 +29,6 @@ void soc_v1_0_grbm_select(struct amdgpu_device *adev,
                          u32 me, u32 pipe,
                          u32 queue, u32 vmid,
                          int xcc_id);
+int soc_v1_0_init_soc_config(struct amdgpu_device *adev);
 
 #endif