testsuite: riscv: pr83403-*.c need common 32bit --param on rv32

Like various other 32-bit CPUs, riscv32 needs to bump the
max-completely-peeled-insns param to 300 to meet the expectations.

for  gcc/testsuite/ChangeLog

	* gcc.dg/tree-ssa/pr83403-1.c: Bump param on riscv32.
	* gcc.dg/tree-ssa/pr83403-2.c: Likewise.

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr83403-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr83403-1.c
index 84646b07cab986b38a714eb5f8f33da6da06e132..f631265edd8e902271b80914fc63feae12106961 100644 (file)
--- a/gcc/testsuite/gcc.dg/tree-ssa/pr83403-1.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr83403-1.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O3 -funroll-loops -fdump-tree-lim2-details" } */
 /* { dg-additional-options "--param max-completely-peeled-insns=200" { target { s390*-*-* } } } */
-/* { dg-additional-options "--param max-completely-peeled-insns=300" { target { arm*-*-* cris-*-* loongarch32-*-* m68k*-*-* } } } */
+/* { dg-additional-options "--param max-completely-peeled-insns=300" { target { { arm*-*-* cris-*-* loongarch32-*-* m68k*-*-* } || rv32 } } } */
 
 #define TYPE unsigned int
 

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr83403-2.c b/gcc/testsuite/gcc.dg/tree-ssa/pr83403-2.c
index 7c830353ea18c645ff1786812927a0e310eccf2f..f14b5b4b5fd0f40dbfd6bd4645b9bb0ec12ad0a6 100644 (file)
--- a/gcc/testsuite/gcc.dg/tree-ssa/pr83403-2.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr83403-2.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O3 -funroll-loops -fdump-tree-lim2-details" } */
 /* { dg-additional-options "--param max-completely-peeled-insns=200" { target { s390*-*-* } } } */
-/* { dg-additional-options "--param max-completely-peeled-insns=300" { target { arm*-*-* cris-*-* loongarch32*-*-* m68k*-*-* } } } */
+/* { dg-additional-options "--param max-completely-peeled-insns=300" { target { { arm*-*-* cris-*-* loongarch32*-*-* m68k*-*-* } || rv32 } } } */
 
 #define TYPE int