The call to set the rounding mode for DFP iops: Iop_AddD128, Iop_SubD128,

Iop_MulD128, Iop_DivD128, and Iop_D128toI64 is wrong. The call being used is
set_FPU_rounding_mode(). This call is used to set the two rounding mode bits
for the Floating point instructions. The call set_FPU_DFP_rounding_mode()
should have been used to set the three rounding mode bits for the DFP
instructions.

This patch changes the call to the correct function to set the DFP
rounding mode bits.

The patch must be applied from the VEX directory.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2627

diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c
index 7b3b2d7334163716b47715c04af4539ce81c659b..486286b86dab6dd6f95789964bd8020656abd14f 100644 (file)
--- a/VEX/priv/host_ppc_isel.c
+++ b/VEX/priv/host_ppc_isel.c
@@ -4109,7 +4109,7 @@ static void iselDfp128Expr_wrk(HReg* rHi, HReg *rLo, ISelEnv* env, IRExpr* e)
          PPCFpOp fpop = Pfp_DRDPQ;
          HReg fr_dst  = newVRegF(env);
 
-         set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
+         set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1 );
          iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2);
          addInstr(env, PPCInstr_DfpD128toD64(fpop, fr_dst, r_srcHi, r_srcLo));
 
@@ -4203,7 +4203,7 @@ static void iselDfp128Expr_wrk(HReg* rHi, HReg *rLo, ISelEnv* env, IRExpr* e)
          /* dst will be used to pass in the left operand and get the result. */
          iselDfp128Expr( &r_dstHi, &r_dstLo, env, triop->arg2 );
          iselDfp128Expr( &r_srcRHi, &r_srcRLo, env, triop->arg3 );
-         set_FPU_rounding_mode( env, triop->arg1 );
+         set_FPU_DFP_rounding_mode( env, triop->arg1 );
          addInstr( env,
                    PPCInstr_Dfp128Binary( fpop, r_dstHi, r_dstLo,
                                           r_srcRHi, r_srcRLo ) );