--- /dev/null
+From 2982f395c9a513b168f1e685588f70013cba2f5f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:14 +0300
+Subject: [PATCH 07/15] net: dsa: mt7530: move MT753X_MTRAP operations for
+ MT7530
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On MT7530, the media-independent interfaces of port 5 and 6 are controlled
+by the MT7530_P5_DIS and MT7530_P6_DIS bits of the hardware trap. Deal with
+these bits only when the relevant port is being enabled or disabled. This
+ensures that these ports will be disabled when they are not in use.
+
+Do not set MT7530_CHG_TRAP on mt7530_setup_port5() as that's already being
+done on mt7530_setup().
+
+Instead of globally setting MT7530_P5_MAC_SEL, clear it, then set it only
+on the appropriate case.
+
+If PHY muxing is detected, clear MT7530_P5_DIS before calling
+mt7530_setup_port5().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 38 +++++++++++++++++++++++++++-----------
+ 1 file changed, 27 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -873,8 +873,7 @@ static void mt7530_setup_port5(struct ds
+
+ val = mt7530_read(priv, MT753X_MTRAP);
+
+- val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
+- val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
++ val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE;
+
+ switch (priv->p5_mode) {
+ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
+@@ -884,15 +883,13 @@ static void mt7530_setup_port5(struct ds
+
+ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
+ case MUX_PHY_P4:
+- val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
+-
+ /* Setup the MAC by default for the cpu port */
+ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ break;
+
+ /* GMAC5: P5 -> SoC MAC or external PHY */
+ default:
+- val &= ~MT7530_P5_DIS;
++ val |= MT7530_P5_MAC_SEL;
+ break;
+ }
+
+@@ -1186,6 +1183,14 @@ mt7530_port_enable(struct dsa_switch *ds
+
+ mutex_unlock(&priv->reg_mutex);
+
++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++ return 0;
++
++ if (port == 5)
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
++ else if (port == 6)
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS);
++
+ return 0;
+ }
+
+@@ -1204,6 +1209,14 @@ mt7530_port_disable(struct dsa_switch *d
+ PCR_MATRIX_CLR);
+
+ mutex_unlock(&priv->reg_mutex);
++
++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++ return;
++
++ if (port == 5)
++ mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
++ else if (port == 6)
++ mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
+ }
+
+ static int
+@@ -2392,11 +2405,11 @@ mt7530_setup(struct dsa_switch *ds)
+ mt7530_rmw(priv, MT7530_TRGMII_RD(i),
+ RD_TAP_MASK, RD_TAP(16));
+
+- /* Enable port 6 */
+- val = mt7530_read(priv, MT753X_MTRAP);
+- val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
+- val |= MT7530_CHG_TRAP;
+- mt7530_write(priv, MT753X_MTRAP, val);
++ /* Allow modifying the trap and directly access PHY registers via the
++ * MDIO bus the switch is on.
++ */
++ mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP |
++ MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP);
+
+ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
+ mt7530_pll_setup(priv);
+@@ -2479,8 +2492,11 @@ mt7530_setup(struct dsa_switch *ds)
+ break;
+ }
+
+- if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
++ if (priv->p5_mode == MUX_PHY_P0 ||
++ priv->p5_mode == MUX_PHY_P4) {
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ mt7530_setup_port5(ds, interface);
++ }
+ }
+
+ #ifdef CONFIG_GPIOLIB
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2642,7 +2642,9 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2658,7 +2658,9 @@ mt7531_setup(struct dsa_switch *ds)
0);
}
/* Setup VLAN ID 0 for VLAN-unaware bridges */
ret = mt7530_setup_vlan0(priv);
-@@ -3001,6 +3003,8 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3017,6 +3019,8 @@ mt753x_setup(struct dsa_switch *ds)
ret = mt7530_setup_mdio(priv);
if (ret && priv->irq)
mt7530_free_irq_common(priv);
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2660,6 +2660,8 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2676,6 +2676,8 @@ mt7531_setup(struct dsa_switch *ds)
static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port,
struct phylink_config *config)
{
switch (port) {
/* Ports which are connected to switch PHYs. There is no MII pinout. */
case 0 ... 4:
-@@ -2691,6 +2693,8 @@ static void mt7531_mac_port_get_caps(str
+@@ -2707,6 +2709,8 @@ static void mt7531_mac_port_get_caps(str
{
struct mt7530_priv *priv = ds->priv;
switch (port) {
/* Ports which are connected to switch PHYs. There is no MII pinout. */
case 0 ... 4:
-@@ -2730,14 +2734,17 @@ static void mt7988_mac_port_get_caps(str
+@@ -2746,14 +2750,17 @@ static void mt7988_mac_port_get_caps(str
case 0 ... 3:
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
config->supported_interfaces);
}
}
-@@ -2907,9 +2914,7 @@ static void mt753x_phylink_get_caps(stru
+@@ -2923,9 +2930,7 @@ static void mt753x_phylink_get_caps(stru
{
struct mt7530_priv *priv = ds->priv;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -3204,13 +3204,6 @@ mt7530_probe_common(struct mt7530_priv *
+@@ -3220,13 +3220,6 @@ mt7530_probe_common(struct mt7530_priv *
if (!priv->info)
return -EINVAL;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -3035,10 +3035,10 @@ static int mt753x_get_mac_eee(struct dsa
+@@ -3048,10 +3048,10 @@ static int mt753x_get_mac_eee(struct dsa
struct ethtool_eee *e)
{
struct mt7530_priv *priv = ds->priv;
return 0;
}
-@@ -3052,11 +3052,11 @@ static int mt753x_set_mac_eee(struct dsa
+@@ -3065,11 +3065,11 @@ static int mt753x_set_mac_eee(struct dsa
if (e->tx_lpi_timer > 0xFFF)
return -EINVAL;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -1398,7 +1398,7 @@ mt7530_port_set_vlan_unaware(struct dsa_
+@@ -1404,7 +1404,7 @@ mt7530_port_set_vlan_unaware(struct dsa_
mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
G0_PORT_VID_DEF);
if (dsa_is_user_port(ds, i) &&
dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
all_user_ports_removed = false;
-@@ -2415,7 +2415,7 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2419,7 +2419,7 @@ mt7530_setup(struct dsa_switch *ds)
/* Enable and reset MIB counters */
mt7530_mib_reset(ds);
/* Clear link settings and enable force mode to force link down
* on all ports until they're enabled later.
*/
-@@ -2523,7 +2523,7 @@ mt7531_setup_common(struct dsa_switch *d
+@@ -2530,7 +2530,7 @@ mt7531_setup_common(struct dsa_switch *d
mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
UNU_FFP_MASK);
/* Clear link settings and enable force mode to force link down
* on all ports until they're enabled later.
*/
-@@ -2610,7 +2610,7 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2617,7 +2617,7 @@ mt7531_setup(struct dsa_switch *ds)
priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
/* Force link down on all ports before internal reset */
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2760,7 +2760,7 @@ mt7530_mac_config(struct dsa_switch *ds,
+@@ -2776,7 +2776,7 @@ mt7530_mac_config(struct dsa_switch *ds,
mt7530_setup_port6(priv->ds, interface);
}
phy_interface_t interface,
struct phy_device *phydev)
{
-@@ -2811,7 +2811,7 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2827,7 +2827,7 @@ mt7531_mac_config(struct dsa_switch *ds,
if (phy_interface_mode_is_rgmii(interface)) {
dp = dsa_to_port(ds, port);
phydev = dp->slave->phydev;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2610,7 +2610,10 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2626,7 +2626,10 @@ mt7531_setup(struct dsa_switch *ds)
if (!priv->p5_sgmii) {
mt7531_pll_setup(priv);
} else {
--- /dev/null
+From 2982f395c9a513b168f1e685588f70013cba2f5f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:14 +0300
+Subject: [PATCH 07/15] net: dsa: mt7530: move MT753X_MTRAP operations for
+ MT7530
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On MT7530, the media-independent interfaces of port 5 and 6 are controlled
+by the MT7530_P5_DIS and MT7530_P6_DIS bits of the hardware trap. Deal with
+these bits only when the relevant port is being enabled or disabled. This
+ensures that these ports will be disabled when they are not in use.
+
+Do not set MT7530_CHG_TRAP on mt7530_setup_port5() as that's already being
+done on mt7530_setup().
+
+Instead of globally setting MT7530_P5_MAC_SEL, clear it, then set it only
+on the appropriate case.
+
+If PHY muxing is detected, clear MT7530_P5_DIS before calling
+mt7530_setup_port5().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 38 +++++++++++++++++++++++++++-----------
+ 1 file changed, 27 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -880,8 +880,7 @@ static void mt7530_setup_port5(struct ds
+
+ val = mt7530_read(priv, MT753X_MTRAP);
+
+- val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
+- val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
++ val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE;
+
+ switch (priv->p5_mode) {
+ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
+@@ -891,15 +890,13 @@ static void mt7530_setup_port5(struct ds
+
+ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
+ case MUX_PHY_P4:
+- val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
+-
+ /* Setup the MAC by default for the cpu port */
+ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ break;
+
+ /* GMAC5: P5 -> SoC MAC or external PHY */
+ default:
+- val &= ~MT7530_P5_DIS;
++ val |= MT7530_P5_MAC_SEL;
+ break;
+ }
+
+@@ -1193,6 +1190,14 @@ mt7530_port_enable(struct dsa_switch *ds
+
+ mutex_unlock(&priv->reg_mutex);
+
++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++ return 0;
++
++ if (port == 5)
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
++ else if (port == 6)
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS);
++
+ return 0;
+ }
+
+@@ -1211,6 +1216,14 @@ mt7530_port_disable(struct dsa_switch *d
+ PCR_MATRIX_CLR);
+
+ mutex_unlock(&priv->reg_mutex);
++
++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++ return;
++
++ if (port == 5)
++ mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
++ else if (port == 6)
++ mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
+ }
+
+ static int
+@@ -2401,11 +2414,11 @@ mt7530_setup(struct dsa_switch *ds)
+ mt7530_rmw(priv, MT7530_TRGMII_RD(i),
+ RD_TAP_MASK, RD_TAP(16));
+
+- /* Enable port 6 */
+- val = mt7530_read(priv, MT753X_MTRAP);
+- val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
+- val |= MT7530_CHG_TRAP;
+- mt7530_write(priv, MT753X_MTRAP, val);
++ /* Allow modifying the trap and directly access PHY registers via the
++ * MDIO bus the switch is on.
++ */
++ mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP |
++ MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP);
+
+ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
+ mt7530_pll_setup(priv);
+@@ -2488,8 +2501,11 @@ mt7530_setup(struct dsa_switch *ds)
+ break;
+ }
+
+- if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
++ if (priv->p5_mode == MUX_PHY_P0 ||
++ priv->p5_mode == MUX_PHY_P4) {
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ mt7530_setup_port5(ds, interface);
++ }
+ }
+
+ #ifdef CONFIG_GPIOLIB
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2651,7 +2651,9 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2667,7 +2667,9 @@ mt7531_setup(struct dsa_switch *ds)
0);
}
/* Setup VLAN ID 0 for VLAN-unaware bridges */
ret = mt7530_setup_vlan0(priv);
-@@ -3004,6 +3006,8 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3020,6 +3022,8 @@ mt753x_setup(struct dsa_switch *ds)
ret = mt7530_setup_mdio(priv);
if (ret && priv->irq)
mt7530_free_irq_common(priv);
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2669,6 +2669,8 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2685,6 +2685,8 @@ mt7531_setup(struct dsa_switch *ds)
static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port,
struct phylink_config *config)
{
switch (port) {
/* Ports which are connected to switch PHYs. There is no MII pinout. */
case 0 ... 4:
-@@ -2700,6 +2702,8 @@ static void mt7531_mac_port_get_caps(str
+@@ -2716,6 +2718,8 @@ static void mt7531_mac_port_get_caps(str
{
struct mt7530_priv *priv = ds->priv;
switch (port) {
/* Ports which are connected to switch PHYs. There is no MII pinout. */
case 0 ... 4:
-@@ -2739,14 +2743,17 @@ static void mt7988_mac_port_get_caps(str
+@@ -2755,14 +2759,17 @@ static void mt7988_mac_port_get_caps(str
case 0 ... 3:
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
config->supported_interfaces);
}
}
-@@ -2916,9 +2923,7 @@ static void mt753x_phylink_get_caps(stru
+@@ -2932,9 +2939,7 @@ static void mt753x_phylink_get_caps(stru
{
struct mt7530_priv *priv = ds->priv;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -3216,13 +3216,6 @@ mt7530_probe_common(struct mt7530_priv *
+@@ -3232,13 +3232,6 @@ mt7530_probe_common(struct mt7530_priv *
if (!priv->info)
return -EINVAL;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -3032,10 +3032,10 @@ static int mt753x_get_mac_eee(struct dsa
+@@ -3051,10 +3051,10 @@ static int mt753x_get_mac_eee(struct dsa
struct ethtool_eee *e)
{
struct mt7530_priv *priv = ds->priv;
return 0;
}
-@@ -3049,11 +3049,11 @@ static int mt753x_set_mac_eee(struct dsa
+@@ -3068,11 +3068,11 @@ static int mt753x_set_mac_eee(struct dsa
if (e->tx_lpi_timer > 0xFFF)
return -EINVAL;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -1391,7 +1391,7 @@ mt7530_port_set_vlan_unaware(struct dsa_
+@@ -1411,7 +1411,7 @@ mt7530_port_set_vlan_unaware(struct dsa_
mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
G0_PORT_VID_DEF);
if (dsa_is_user_port(ds, i) &&
dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
all_user_ports_removed = false;
-@@ -2406,7 +2406,7 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2428,7 +2428,7 @@ mt7530_setup(struct dsa_switch *ds)
/* Enable and reset MIB counters */
mt7530_mib_reset(ds);
/* Clear link settings and enable force mode to force link down
* on all ports until they're enabled later.
*/
-@@ -2514,7 +2514,7 @@ mt7531_setup_common(struct dsa_switch *d
+@@ -2539,7 +2539,7 @@ mt7531_setup_common(struct dsa_switch *d
mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
UNU_FFP_MASK);
/* Clear link settings and enable force mode to force link down
* on all ports until they're enabled later.
*/
-@@ -2601,7 +2601,7 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2626,7 +2626,7 @@ mt7531_setup(struct dsa_switch *ds)
priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
/* Force link down on all ports before internal reset */
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2769,7 +2769,7 @@ mt7530_mac_config(struct dsa_switch *ds,
+@@ -2785,7 +2785,7 @@ mt7530_mac_config(struct dsa_switch *ds,
mt7530_setup_port6(priv->ds, interface);
}
phy_interface_t interface,
struct phy_device *phydev)
{
-@@ -2820,7 +2820,7 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2836,7 +2836,7 @@ mt7531_mac_config(struct dsa_switch *ds,
if (phy_interface_mode_is_rgmii(interface)) {
dp = dsa_to_port(ds, port);
phydev = dp->slave->phydev;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2619,7 +2619,10 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2635,7 +2635,10 @@ mt7531_setup(struct dsa_switch *ds)
if (!priv->p5_sgmii) {
mt7531_pll_setup(priv);
} else {
--- /dev/null
+From patchwork Sat Apr 27 11:24:42 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 8bit
+X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?=
+ <devnull+arinc.unal.arinc9.com@kernel.org>
+X-Patchwork-Id: 13645655
+From: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?=
+ <devnull+arinc.unal.arinc9.com@kernel.org>
+Date: Sat, 27 Apr 2024 14:24:42 +0300
+Subject: [PATCH net-next] net: dsa: mt7530: do not set MT7530_P5_DIS when
+ PHY muxing is being used
+Precedence: bulk
+X-Mailing-List: netdev@vger.kernel.org
+List-Id: <netdev.vger.kernel.org>
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+Message-Id:
+ <20240427-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-v1-1-793cdf9d7707@arinc9.com>
+To: Daniel Golle <daniel@makrotopia.org>, DENG Qingfang <dqfext@gmail.com>,
+ Sean Wang <sean.wang@mediatek.com>, Andrew Lunn <andrew@lunn.ch>,
+ Florian Fainelli <f.fainelli@gmail.com>,
+ Vladimir Oltean <olteanv@gmail.com>,
+ "David S. Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>,
+ Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
+ Matthias Brugger <matthias.bgg@gmail.com>,
+ AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org,
+ =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>
+X-Mailer: b4 0.13.0
+X-Patchwork-Delegate: kuba@kernel.org
+
+From: Arınç ÜNAL <arinc.unal@arinc9.com>
+
+When the PHY muxing feature is in use, port 5 won't be defined in the
+device tree. Because of this, the type member of the dsa_port structure for
+this port will be assigned DSA_PORT_TYPE_UNUSED. The dsa_port_setup()
+function calls ds->ops->port_disable() when the port type is
+DSA_PORT_TYPE_UNUSED.
+
+The MT7530_P5_DIS bit is unset when PHY muxing is being used.
+mt7530_port_disable() which is assigned to ds->ops->port_disable() is
+called afterwards. Currently, mt7530_port_disable() sets MT7530_P5_DIS
+which breaks network connectivity when PHY muxing is being used.
+
+Therefore, do not set MT7530_P5_DIS when PHY muxing is being used.
+
+Fixes: 377174c5760c ("net: dsa: mt7530: move MT753X_MTRAP operations for MT7530")
+Reported-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+Hello.
+
+I've sent this to net-next as the patch it fixes is on the current
+development cycle.
+---
+ drivers/net/dsa/mt7530.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+
+---
+base-commit: 5c4c0edca68a5841a8d53ccd49596fe199c8334c
+change-id: 20240427-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-7ff5fd0995d7
+
+Best regards,
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1213,7 +1213,7 @@ mt7530_port_disable(struct dsa_switch *d
+ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
+ return;
+
+- if (port == 5)
++ if (port == 5 && priv->p5_mode == GMAC5)
+ mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ else if (port == 6)
+ mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
--- /dev/null
+From patchwork Sat Apr 27 11:24:42 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 8bit
+X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?=
+ <devnull+arinc.unal.arinc9.com@kernel.org>
+X-Patchwork-Id: 13645655
+From: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?=
+ <devnull+arinc.unal.arinc9.com@kernel.org>
+Date: Sat, 27 Apr 2024 14:24:42 +0300
+Subject: [PATCH net-next] net: dsa: mt7530: do not set MT7530_P5_DIS when
+ PHY muxing is being used
+Precedence: bulk
+X-Mailing-List: netdev@vger.kernel.org
+List-Id: <netdev.vger.kernel.org>
+List-Subscribe: <mailto:netdev+subscribe@vger.kernel.org>
+List-Unsubscribe: <mailto:netdev+unsubscribe@vger.kernel.org>
+MIME-Version: 1.0
+Message-Id:
+ <20240427-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-v1-1-793cdf9d7707@arinc9.com>
+To: Daniel Golle <daniel@makrotopia.org>, DENG Qingfang <dqfext@gmail.com>,
+ Sean Wang <sean.wang@mediatek.com>, Andrew Lunn <andrew@lunn.ch>,
+ Florian Fainelli <f.fainelli@gmail.com>,
+ Vladimir Oltean <olteanv@gmail.com>,
+ "David S. Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>,
+ Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
+ Matthias Brugger <matthias.bgg@gmail.com>,
+ AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org,
+ =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>
+X-Mailer: b4 0.13.0
+X-Patchwork-Delegate: kuba@kernel.org
+
+From: Arınç ÜNAL <arinc.unal@arinc9.com>
+
+When the PHY muxing feature is in use, port 5 won't be defined in the
+device tree. Because of this, the type member of the dsa_port structure for
+this port will be assigned DSA_PORT_TYPE_UNUSED. The dsa_port_setup()
+function calls ds->ops->port_disable() when the port type is
+DSA_PORT_TYPE_UNUSED.
+
+The MT7530_P5_DIS bit is unset when PHY muxing is being used.
+mt7530_port_disable() which is assigned to ds->ops->port_disable() is
+called afterwards. Currently, mt7530_port_disable() sets MT7530_P5_DIS
+which breaks network connectivity when PHY muxing is being used.
+
+Therefore, do not set MT7530_P5_DIS when PHY muxing is being used.
+
+Fixes: 377174c5760c ("net: dsa: mt7530: move MT753X_MTRAP operations for MT7530")
+Reported-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+Hello.
+
+I've sent this to net-next as the patch it fixes is on the current
+development cycle.
+---
+ drivers/net/dsa/mt7530.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+
+---
+base-commit: 5c4c0edca68a5841a8d53ccd49596fe199c8334c
+change-id: 20240427-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-7ff5fd0995d7
+
+Best regards,
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1220,7 +1220,7 @@ mt7530_port_disable(struct dsa_switch *d
+ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
+ return;
+
+- if (port == 5)
++ if (port == 5 && priv->p5_mode == GMAC5)
+ mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ else if (port == 6)
+ mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
projects / thirdparty / openwrt.git / commitdiff
