PCI: intel-gw: Enable clock before PHY init

To ensure that the boot sequence is correct, the DWC PCIe core clock must
be switched on before PHY init call [1]. This changes are based on patched
kernel sources of the MaxLinear SDK.

The reason why the MaxLinear SDK is used as a reference here is, that this
PCIe DWC IP is used in the URX851 and URX850 SoC. This SoC was originally
developed by Intel when they acquired Lantiq’s home networking division in
2015 [2]. In 2020 the home network division was sold to MaxLinear [3].
Since then, this SoC belongs to MaxLinear. They use their own SDK, which
runs on kernel version '5.15.x'.

[1] https://github.com/maxlinear/linux/blob/updk_9.1.90/drivers/pci/controller/dwc/pcie-intel-gw.c#L544
[2] https://www.intc.com/news-events/press-releases/detail/364/intel-to-acquire-lantiq-advancing-the-connected-home
[3] https://investors.maxlinear.com/press-releases/detail/395/maxlinear-to-acquire-intels-home-gateway-platform

Signed-off-by: Florian Eckert <fe@dev.tdt.de>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260417-pcie-intel-gw-v5-4-0a2b933fe04f@dev.tdt.de

diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index e88b8243cc41c607c39e4d58c4dcd8c8c082e8b0..6d9499d954674a26a74bff56b7fb5759767424c0 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -291,13 +291,9 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)
 
        intel_pcie_core_rst_assert(pcie);
        intel_pcie_device_rst_assert(pcie);
-
-       ret = phy_init(pcie->phy);
-       if (ret)
-               return ret;
-
        intel_pcie_core_rst_deassert(pcie);
 
+       /* Controller clock must be provided earlier than PHY */
        ret = clk_prepare_enable(pcie->core_clk);
        if (ret) {
                dev_err(pcie->pci.dev, "Core clock enable failed: %d\n", ret);
@@ -306,13 +302,17 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)
 
        pci->atu_base = pci->dbi_base + 0xC0000;
 
+       ret = phy_init(pcie->phy);
+       if (ret)
+               goto phy_err;
+
        intel_pcie_ltssm_disable(pcie);
        intel_pcie_link_setup(pcie);
        intel_pcie_init_n_fts(pci);
 
        ret = dw_pcie_setup_rc(&pci->pp);
        if (ret)
-               goto app_init_err;
+               goto err;
 
        dw_pcie_upconfig_setup(pci);
 
@@ -321,17 +321,18 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)
 
        ret = dw_pcie_wait_for_link(pci);
        if (ret)
-               goto app_init_err;
+               goto err;
 
        intel_pcie_core_irq_enable(pcie);
 
        return 0;
 
-app_init_err:
+err:
+       phy_exit(pcie->phy);
+phy_err:
        clk_disable_unprepare(pcie->core_clk);
 clk_err:
        intel_pcie_core_rst_assert(pcie);
-       phy_exit(pcie->phy);
 
        return ret;
 }