arm64: dts: imx95: Add SMMU PMU nodes

MMU-700 supports TCU PMU and TBU PMU. There are one TCU PMU and
11 TBU PMUs, add them all.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 28b19a47a59daaff308fecce6e7b9ffe14133f74..3e35c956a4d7af88310b3dfaef7e3d064f530e07 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -1770,6 +1770,90 @@
                                #iommu-cells = <1>;
                                status = "disabled";
                        };
+
+                       pmu@490d2000 {
+                               compatible = "arm,smmu-v3-pmcg";
+                               reg = <0x490d2000 0x1000>,
+                                     <0x490f2000 0x1000>;
+                               interrupts = <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
+                       };
+
+                       pmu@49112000 {
+                               compatible = "arm,smmu-v3-pmcg";
+                               reg = <0x49112000 0x1000>,
+                                     <0x49122000 0x1000>;
+                               interrupts = <GIC_SPI 323 IRQ_TYPE_EDGE_RISING>;
+                       };
+
+                       pmu@49132000 {
+                               compatible = "arm,smmu-v3-pmcg";
+                               reg = <0x49132000 0x1000>,
+                                     <0x49142000 0x1000>;
+                               interrupts = <GIC_SPI 323 IRQ_TYPE_EDGE_RISING>;
+                       };
+
+                       pmu@49152000 {
+                               compatible = "arm,smmu-v3-pmcg";
+                               reg = <0x49152000 0x1000>,
+                                     <0x49162000 0x1000>;
+                               interrupts = <GIC_SPI 323 IRQ_TYPE_EDGE_RISING>;
+                       };
+
+                       pmu@49172000 {
+                               compatible = "arm,smmu-v3-pmcg";
+                               reg = <0x49172000 0x1000>,
+                                     <0x49182000 0x1000>;
+                               interrupts = <GIC_SPI 323 IRQ_TYPE_EDGE_RISING>;
+                       };
+
+                       pmu@49192000 {
+                               compatible = "arm,smmu-v3-pmcg";
+                               reg = <0x49192000 0x1000>,
+                                     <0x491a2000 0x1000>;
+                               interrupts = <GIC_SPI 323 IRQ_TYPE_EDGE_RISING>;
+                       };
+
+                       pmu@491b2000 {
+                               compatible = "arm,smmu-v3-pmcg";
+                               reg = <0x491b2000 0x1000>,
+                                     <0x491c2000 0x1000>;
+                               interrupts = <GIC_SPI 323 IRQ_TYPE_EDGE_RISING>;
+                       };
+
+                       pmu@491d2000 {
+                               compatible = "arm,smmu-v3-pmcg";
+                               reg = <0x491d2000 0x1000>,
+                                     <0x491e2000 0x1000>;
+                               interrupts = <GIC_SPI 323 IRQ_TYPE_EDGE_RISING>;
+                       };
+
+                       pmu@491f2000 {
+                               compatible = "arm,smmu-v3-pmcg";
+                               reg = <0x491f2000 0x1000>,
+                                     <0x49202000 0x1000>;
+                               interrupts = <GIC_SPI 323 IRQ_TYPE_EDGE_RISING>;
+                       };
+
+                       pmu@49212000 {
+                               compatible = "arm,smmu-v3-pmcg";
+                               reg = <0x49212000 0x1000>,
+                                     <0x49222000 0x1000>;
+                               interrupts = <GIC_SPI 323 IRQ_TYPE_EDGE_RISING>;
+                       };
+
+                       pmu@49232000 {
+                               compatible = "arm,smmu-v3-pmcg";
+                               reg = <0x49232000 0x1000>,
+                                     <0x49242000 0x1000>;
+                               interrupts = <GIC_SPI 323 IRQ_TYPE_EDGE_RISING>;
+                       };
+
+                       pmu@49252000 {
+                               compatible = "arm,smmu-v3-pmcg";
+                               reg = <0x49252000 0x1000>,
+                                     <0x49262000 0x1000>;
+                               interrupts = <GIC_SPI 323 IRQ_TYPE_EDGE_RISING>;
+                       };
                };
 
                usb3: usb@4c010010 {