Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8c40001b361cf6fdf81f1fb51bcba738a2d86b10..17c9a0443ff3310e86eb8075003350e3f5677a3c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,102 @@
+2025-07-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2025-07-11  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR target/121027
+       * config/aarch64/aarch64.cc (aarch64_evpc_sve_tbl): Punt on 2-input
+       operations that can be handled by vec_perm.
+
+2025-07-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2025-07-10  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64-sve2.md (aarch64_gather_ld1q): Replace with...
+       (@aarch64_gather_ld1q<mode>): ...this, parameterizing based on mode.
+       * config/aarch64/aarch64-sve-builtins-sve2.cc
+       (svld1q_gather_impl::expand): Update accordingly.
+       (svst1q_scatter_impl::expand): Use aarch64_sve_reinterpret
+       instead of force_lowpart_subreg.
+
+2025-07-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2025-07-10  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * doc/sourcebuild.texi (aarch64_sve2_hw, aarch64_sve2p1_hw): Document.
+       * config/aarch64/aarch64.cc (aarch64_evpc_hvla): Extend to
+       BYTES_BIG_ENDIAN.
+
+2025-07-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2025-07-09  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64.cc (aarch64_simd_valid_imm): Account
+       for FLOAT_WORDS_BIG_ENDIAN when building a floating-point value.
+
+2025-07-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2025-07-09  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64.cc (aarch64_sve_index_series_p): New
+       function, split out from...
+       (aarch64_simd_valid_imm): ...here.  Account for the different
+       SVE and Advanced SIMD element orders on big-endian targets.
+       Check each vector in a structure mode.
+
+2025-07-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2025-07-09  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * read-rtl-function.cc (function_reader::read_rtx_operand_r): Use
+       hard_regno_nregs to work out REG_NREGS for hard registers.
+
+2025-07-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2025-07-09  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * ext-dce.cc (ext_dce_process_uses): Apply is_constant directly
+       to the subreg_lsb.
+
+2025-07-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2025-07-07  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR target/118891
+       * config/aarch64/aarch64.cc (aarch64_expand_vector_init): Fix the
+       ZIP1 operand order for big-endian targets.
+
+2025-07-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2025-07-07  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64-sve.md (@aarch64_sve_set_neonq_<mode>):
+       Use %Z instead of lowpart_subreg.  Tweak formatting.
+
+2025-07-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2025-07-07  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * ext-dce.cc (ext_dce_process_uses): Apply is_constant directly
+       to the subreg_lsb.
+
+2025-07-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2025-07-07  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR tree-optimization/118891
+       * tree-vect-stmts.cc (supportable_widening_operation): Swap the
+       hi and lo internal functions on big-endian targets.
+
 2025-07-18  Hans-Peter Nilsson  <hp@bitrange.com>
            Pietro Monteiro  <pietro@sociotechnical.xyz>
 

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b1af684c29057bc4e6ac034c3ca93f4641768f5c..7578d8939d61cb462c1a4670bfdd0bc4c280cf3c 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250721
+20250722

diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
index d61c51eae1f7e492f379496e611f351bdb4e0a99..759f05495a8c8745216bb3223fe76c0f5ea0e64a 100644 (file)
--- a/gcc/ada/ChangeLog
+++ b/gcc/ada/ChangeLog
@@ -1,3 +1,8 @@
+2025-07-21  Eric Botcazou  <ebotcazou@gcc.gnu.org>
+
+       PR ada/121184
+       * styleg.adb (Check_Comment): Use consistent warning message.
+
 2025-07-14  Eric Botcazou  <ebotcazou@adacore.com>
 
        PR ada/121056

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 76dbf4361d8d1515d7751ce004622591ad56cf06..66bf434f51da3e8e86caf945a2f98af3eb8bae60 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,111 @@
+2025-07-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2025-07-11  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR target/121027
+       * gcc.target/aarch64/sve/acle/general/perm_1.c: New test.
+
+2025-07-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2025-07-10  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * gcc.target/aarch64/sve/pfalse-binary.c: Add -funwind-tables.
+       * gcc.target/aarch64/sve/pfalse-binary_int_opt_n.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-binary_opt_n.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-binary_opt_single_n.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-binary_rotate.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-binary_uint64_opt_n.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-binary_uint_opt_n.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-binaryxn.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-clast.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-compare_opt_n.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-compare_wide_opt_n.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-count_pred.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-fold_left.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-load.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-load_ext.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-load_ext_gather_index.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-load_ext_gather_offset.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-load_gather_sv.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-load_gather_vs.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-load_replicate.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-prefetch.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-prefetch_gather_index.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-prefetch_gather_offset.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-ptest.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-rdffr.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-reduction.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-reduction_wide.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-shift_right_imm.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-store.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-store_scatter_index.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-store_scatter_offset.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-storexn.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-ternary_opt_n.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-ternary_rotate.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-unary.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-unary_convert_narrowt.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-unary_convertxn.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-unary_n.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-unary_pred.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-unary_to_uint.c: Likewise.
+       * gcc.target/aarch64/sve/pfalse-unaryxn.c: Likewise.
+       * gcc.target/aarch64/sve2/pfalse-binary.c: Likewise.
+       * gcc.target/aarch64/sve2/pfalse-binary_int_opt_n.c: Likewise.
+       * gcc.target/aarch64/sve2/pfalse-binary_int_opt_single_n.c: Likewise.
+       * gcc.target/aarch64/sve2/pfalse-binary_opt_n.c: Likewise.
+       * gcc.target/aarch64/sve2/pfalse-binary_opt_single_n.c: Likewise.
+       * gcc.target/aarch64/sve2/pfalse-binary_to_uint.c: Likewise.
+       * gcc.target/aarch64/sve2/pfalse-binary_uint_opt_n.c: Likewise.
+       * gcc.target/aarch64/sve2/pfalse-binary_wide.c: Likewise.
+       * gcc.target/aarch64/sve2/pfalse-compare.c: Likewise.
+       * gcc.target/aarch64/sve2/pfalse-load_ext_gather_index_restricted.c,
+       * gcc.target/aarch64/sve2/pfalse-load_ext_gather_offset_restricted.c,
+       * gcc.target/aarch64/sve2/pfalse-load_gather_sv_restricted.c: Likewise.
+       * gcc.target/aarch64/sve2/pfalse-load_gather_vs.c: Likewise.
+       * gcc.target/aarch64/sve2/pfalse-shift_left_imm_to_uint.c: Likewise.
+       * gcc.target/aarch64/sve2/pfalse-shift_right_imm.c: Likewise.
+       * gcc.target/aarch64/sve2/pfalse-store_scatter_index_restricted.c,
+       * gcc.target/aarch64/sve2/pfalse-store_scatter_offset_restricted.c,
+       * gcc.target/aarch64/sve2/pfalse-unary.c: Likewise.
+       * gcc.target/aarch64/sve2/pfalse-unary_convert.c: Likewise.
+       * gcc.target/aarch64/sve2/pfalse-unary_convert_narrowt.c: Likewise.
+       * gcc.target/aarch64/sve2/pfalse-unary_to_int.c: Likewise.
+
+2025-07-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2025-07-10  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * lib/target-supports.exp (check_effective_target_aarch64_sve2p1_hw):
+       New proc.
+       * gcc.target/aarch64/sve2/dupq_1.c: Extend to big-endian.  Add
+       noipa attributes.
+       * gcc.target/aarch64/sve2/extq_1.c: Likewise.
+       * gcc.target/aarch64/sve2/uzpq_1.c: Likewise.
+       * gcc.target/aarch64/sve2/zipq_1.c: Likewise.
+       * gcc.target/aarch64/sve2/dupq_1_run.c: New test.
+       * gcc.target/aarch64/sve2/extq_1_run.c: Likewise.
+       * gcc.target/aarch64/sve2/uzpq_1_run.c: Likewise.
+       * gcc.target/aarch64/sve2/zipq_1_run.c: Likewise.
+
+2025-07-21  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2025-07-09  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * gcc.dg/rtl/aarch64/vec-series-1.c: New test.
+       * gcc.dg/rtl/aarch64/vec-series-2.c: Likewise.
+       * gcc.target/aarch64/sve/acle/general/dupq_2.c: Fix expected
+       output for this big-endian test.
+       * gcc.target/aarch64/sve/acle/general/dupq_4.c: Likewise.
+       * gcc.target/aarch64/sve/vec_init_3.c: Restrict to little-endian
+       targets and add more tests.
+       * gcc.target/aarch64/sve/vec_init_4.c: New big-endian version
+       of vec_init_3.c.
+
 2025-07-20  Harald Anlauf  <anlauf@gmx.de>
 
        Backported from master: