# <https://wireless.wiki.kernel.org/en/users/drivers/ath10k/boardfiles>
ALLWIFIBOARDS:= \
+ 8devices_kiwi \
8devices_mango \
alfa-network_ap120c-ax \
aliyun_ap8220 \
SUBMENU:=ath10k Board-Specific Overrides
SECTION:=firmware
CATEGORY:=Firmware
- DEPENDS:=@(TARGET_ath79||TARGET_ipq40xx||TARGET_ipq806x||TARGET_qualcommax)
+ DEPENDS:=@(TARGET_ath79||TARGET_ipq40xx||TARGET_ipq806x||TARGET_qualcommax||TARGET_qualcommbe)
TITLE:=Custom Board
endef
$(INSTALL_DATA) $(1) $(2)/lib/firmware/ath11k/$(3)/board-2.bin
endef
+define ipq-wifi-install-ath12-one-to
+ $(INSTALL_DIR) $(2)/lib/firmware/ath12k/$(3)/
+ $(INSTALL_DATA) $(1) $(2)/lib/firmware/ath12k/$(3)/board-2.bin
+endef
+
define ipq-wifi-install-one
$(if $(filter $(suffix $(1)),.QCA4019 .qca4019),\
$(call ipq-wifi-install-one-to,$(1),$(2),QCA4019/hw1.0),\
$(call ipq-wifi-install-ath11-one-to,$(1),$(2),QCN6122/hw1.0),\
$(if $(filter $(suffix $(1)),.QCN9074 .qcn9074),\
$(call ipq-wifi-install-ath11-one-to,$(1),$(2),QCN9074/hw1.0),\
+ $(if $(filter $(suffix $(1)),.QCN9274 .qcn9274),\
+ $(call ipq-wifi-install-ath12-one-to,$(1),$(2),QCN9274/hw2.0),\
$(error Unrecognized board-file suffix '$(suffix $(1))' for '$(1)')\
- ))))))))))
+ )))))))))))
endef
# Blank line required at end of above define due to foreach context
# Board files should follow this name structure:
# board-<devicename>.<qca4019|qca9888|qca9889|qca9984|qca99x0|ipq6018|ipq8074>
+$(eval $(call generate-ipq-wifi-package,8devices_kiwi,8devices Kiwi))
$(eval $(call generate-ipq-wifi-package,8devices_mango,8devices Mango))
$(eval $(call generate-ipq-wifi-package,alfa-network_ap120c-ax,ALFA Network AP120C-AX))
$(eval $(call generate-ipq-wifi-package,aliyun_ap8220,Aliyun AP8220))
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "ipq9574.dtsi"
+
+/ {
+ model = "8devices Kiwi-DVK";
+ compatible = "8devices,kiwi-dvk", "qcom,ipq9574";
+
+ aliases {
+ serial0 = &blsp1_uart2;
+ ethernet0 = &xgmac1;
+ ethernet1 = &xgmac5;
+ ethernet2 = &xgmac6;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ regulator_fixed_3p3: s3300 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-name = "fixed_3p3";
+ };
+
+ regulator_fixed_0p925: s0925 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <925000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-name = "fixed_0p925";
+ };
+
+ sfp0: sfp-0 {
+ compatible = "sff,sfp";
+ pinctrl-0 = <&sfp0_default>;
+ pinctrl-names = "default";
+ i2c-bus = <&blsp1_i2c1>;
+ los-gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&blsp1_i2c1 {
+ pinctrl-0 = <&i2c1_default>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&blsp1_spi0 {
+ pinctrl-0 = <&spi_0_default>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&blsp1_uart2 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&qcom_ppe {
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ xgmac1: port@1 {
+ reg = <1>;
+ phy-mode = "10gbase-r";
+ managed = "in-band-status";
+ label = "wan";
+ sfp = <&sfp0>;
+ pcs-handle = <&pcsuniphy0_ch0>;
+ local-mac-address = [00 00 00 00 00 00];
+ clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>,
+ <&nsscc NSS_CC_PORT1_RX_CLK>,
+ <&nsscc NSS_CC_PORT1_TX_CLK>;
+ clock-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ resets = <&nsscc PORT1_MAC_ARES>,
+ <&nsscc PORT1_RX_ARES>,
+ <&nsscc PORT1_TX_ARES>;
+ reset-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ };
+
+ xgmac5: port@5 {
+ reg = <5>;
+ phy-mode = "2500base-x";
+ label = "lan1";
+ phy-handle = <&phy0>;
+ pcs-handle = <&pcsuniphy1_ch0>;
+ local-mac-address = [00 00 00 00 00 00];
+ clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>,
+ <&nsscc NSS_CC_PORT5_RX_CLK>,
+ <&nsscc NSS_CC_PORT5_TX_CLK>;
+ clock-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ resets = <&nsscc PORT5_MAC_ARES>,
+ <&nsscc PORT5_RX_ARES>,
+ <&nsscc PORT5_TX_ARES>;
+ reset-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ };
+
+ xgmac6: port@6 {
+ reg = <6>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ label = "lan2";
+ phy-handle = <&phy1>;
+ pcs-handle = <&pcsuniphy2_ch0>;
+ local-mac-address = [00 00 00 00 00 00];
+ clocks = <&nsscc NSS_CC_PORT6_MAC_CLK>,
+ <&nsscc NSS_CC_PORT6_RX_CLK>,
+ <&nsscc NSS_CC_PORT6_TX_CLK>;
+ clock-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ resets = <&nsscc PORT6_MAC_ARES>,
+ <&nsscc PORT6_RX_ARES>,
+ <&nsscc PORT6_TX_ARES>;
+ reset-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ phy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <1>;
+ reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+ };
+
+ phy1: ethernet-phy@28 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <28>;
+ reset-assert-us = <40>;
+ reset-deassert-us = <150000>;
+ reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pcie0 {
+ pinctrl-0 = <&pcie0_default>;
+ pinctrl-names = "default";
+
+ perst-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie0_phy {
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-0 = <&pcie1_default>;
+ pinctrl-names = "default";
+
+ perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie1_phy {
+ status = "okay";
+};
+
+&pcie2 {
+ pinctrl-0 = <&pcie2_default>;
+ pinctrl-names = "default";
+
+ perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie2_phy {
+ status = "okay";
+};
+
+&pcie3 {
+ pinctrl-0 = <&pcie3_default>;
+ pinctrl-names = "default";
+
+ perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie3_phy {
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-mp5496-regulators";
+
+ ipq9574_s1: s1 {
+ /*
+ * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
+ * During regulator registration, kernel not knowing the initial voltage,
+ * considers it as zero and brings up the regulators with minimum supported voltage.
+ * Update the regulator-min-microvolt with SVS voltage of 725mV so that
+ * the regulators are brought up with 725mV which is sufficient for all the
+ * corner parts to operate at 800MHz
+ */
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1075000>;
+ };
+
+ mp5496_l5: l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+};
+
+&sdhc_1 {
+ bus-width = <8>;
+ max-frequency = <384000000>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ pinctrl-0 = <&sdc_default_state>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&tlmm {
+ sdc_default_state: sdc-default-state {
+ clk-pins {
+ pins = "gpio5";
+ function = "sdc_clk";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "gpio4";
+ function = "sdc_cmd";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "gpio0", "gpio1", "gpio2",
+ "gpio3", "gpio6", "gpio7",
+ "gpio8", "gpio9";
+ function = "sdc_data";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ rclk-pins {
+ pins = "gpio10";
+ function = "sdc_rclk";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+ };
+
+ spi_0_default: spi-0-default-state {
+ pins = "gpio11", "gpio12", "gpio13", "gpio14";
+ function = "blsp0_spi";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ pcie0_default: pcie0-default-state {
+ clkreq-n-pins {
+ pins = "gpio22";
+ function = "pcie0_clk";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio23";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ output-low;
+ };
+
+ wake-n-pins {
+ pins = "gpio24";
+ function = "pcie0_wake";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_default: pcie1-default-state {
+ clkreq-n-pins {
+ pins = "gpio25";
+ function = "pcie1_clk";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio26";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ output-low;
+ };
+
+ wake-n-pins {
+ pins = "gpio27";
+ function = "pcie1_wake";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+ };
+
+ pcie2_default: pcie2-default-state {
+ clkreq-n-pins {
+ pins = "gpio28";
+ function = "pcie2_clk";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio29";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ output-low;
+ };
+
+ wake-n-pins {
+ pins = "gpio30";
+ function = "pcie2_wake";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+ };
+
+ pcie3_default: pcie3-default-state {
+ clkreq-n-pins {
+ pins = "gpio31";
+ function = "pcie3_clk";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio32";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ output-low;
+ };
+
+ wake-n-pins {
+ pins = "gpio33";
+ function = "pcie3_wake";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+ };
+
+ i2c1_default: i2c1-default-state {
+ pins = "gpio36", "gpio37";
+ function = "blsp1_i2c";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ sfp0_default: sfp0-default-state {
+ pins = "gpio46", "gpio47";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+};
+
+&usb_0_dwc3 {
+ dr_mode = "host";
+};
+
+&usb_0_qmpphy {
+ vdda-pll-supply = <&mp5496_l5>;
+ vdda-phy-supply = <®ulator_fixed_0p925>;
+
+ status = "okay";
+};
+
+&usb_0_qusbphy {
+ vdd-supply = <®ulator_fixed_0p925>;
+ vdda-pll-supply = <&mp5496_l5>;
+ vdda-phy-dpdm-supply = <®ulator_fixed_3p3>;
+
+ status = "okay";
+};
+
+&usb3 {
+ status = "okay";
+};
+
+/*
+ * The bootstrap pins for the board select the XO clock frequency,
+ * which automatically enables the right dividers to ensure the
+ * reference clock output from WiFi is 48 MHZ.
+ */
+&ref_48mhz_clk {
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+/*
+ * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed
+ * from WiFi output clock 48 MHZ divided by 2.
+ */
+&xo_board_clk {
+ clock-div = <2>;
+ clock-mult = <1>;
+};
+
+&xo_clk {
+ clock-frequency = <48000000>;
+};
projects / thirdparty / openwrt.git / commitdiff
