-From 0e1a71d84585ec33b479c2cb8c8d65a4f6734dbe Mon Sep 17 00:00:00 2001
-From: Thomas Richard <thomas.richard@bootlin.com>
-Date: Wed, 4 Dec 2024 14:26:52 +0100
-Subject: [PATCH] Revert "feat(stm32mp1-fdts): remove RTC clock configuration"
+From 33573ea6842198cfdb5b3fdd320db9e2045855e9 Mon Sep 17 00:00:00 2001
+From: Valentin Caron <valentin.caron@foss.st.com>
+Date: Wed, 11 Dec 2024 11:20:04 +0100
+Subject: [PATCH] fix(stm32mp1-fdts): re-enable RTC clock
-This reverts commit 703a581e2522bffe21b421c98994dc02aed2934c.
+On STM32MP15 ST boards, RTC clock configuration by OPTEE is not ready
+yet. Re-enable it temporary to get LSE as clock source of RTC.
+
+Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
+Change-Id: Ib6071229552e456faffb4fdfc8db9808140d54a7
---
- fdts/stm32mp135f-dk.dts | 2 ++
fdts/stm32mp157c-ed1.dts | 2 ++
fdts/stm32mp15xx-dkx.dtsi | 2 ++
- 3 files changed, 6 insertions(+)
+ 2 files changed, 4 insertions(+)
---- a/fdts/stm32mp135f-dk.dts
-+++ b/fdts/stm32mp135f-dk.dts
-@@ -190,6 +190,7 @@
- CLK_AXI_PLL2P
- CLK_MLAHBS_PLL3
- CLK_CKPER_HSE
-+ CLK_RTC_LSE
- CLK_SDMMC1_PLL4P
- CLK_SDMMC2_PLL4P
- CLK_STGEN_HSE
-@@ -211,6 +212,7 @@
- DIV(DIV_APB4, 1)
- DIV(DIV_APB5, 2)
- DIV(DIV_APB6, 1)
-+ DIV(DIV_RTC, 0)
- >;
-
- st,pll_vco {
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@@ -194,6 +194,7 @@