realtek: mdio: rtl838x: activate combo PHY media detection

There is a misunderstanding about BIT(7) aka EX_PHY_MAN_24_27 in
SMI_GLB_CTRL register. The SDK sets/clears it at different places and
it is not clear what it is for. Observation shows that it is essential
for a working MAC_LINK_MEDIA_STS register.

A RTL838x device has usally two configurations

- port 24/26 are 2 serdes driven fiber ports
- port 24-27 are 4 PHY driven combo ports

In the combo case the above bit must be set so that a switch between
copper and fiber can be detected. Cleanup the MDIO initialization
and remove the unneeded bit handling in the DSA driver.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21653
Signed-off-by: Robert Marko <robimarko@gmail.com>

diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c
index 373ab3728d2b73c52e82728223ac74f16e527d28..7c1ab5e0542cb0d6bffd91dc009b5ab3d421cb6d 100644 (file)
--- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c
+++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c
@@ -368,8 +368,8 @@ static int rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
 
        /* Enable PHY control via SoC */
        if (priv->family_id == RTL8380_FAMILY_ID) {
-               /* Enable SerDes NWAY and PHY control via SoC */
-               sw_w32_mask(BIT(7), BIT(15), RTL838X_SMI_GLB_CTRL);
+               /* Enable PHY control by telling SoC that "PHY patching is done" */
+               sw_w32_mask(0, BIT(15), RTL838X_SMI_GLB_CTRL);
        } else if (priv->family_id == RTL8390_FAMILY_ID) {
                /* Disable PHY polling via SoC */
                sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);

diff --git a/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c b/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c
index 44216fe2d98145e76b914ce0cfa3ec31af8942d2..896a08652c86a42f587b016d5c925dbdf87d8320 100644 (file)
--- a/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c
+++ b/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c
@@ -841,14 +841,21 @@ static void rtmdio_get_phy_info(struct mii_bus *bus, int addr, struct rtmdio_phy
 
 static int rtmdio_838x_reset(struct mii_bus *bus)
 {
-       pr_debug("%s called\n", __func__);
-       /* Disable MAC polling the PHY so that we can start configuration */
-       sw_w32(0x00000000, RTMDIO_838X_SMI_POLL_CTRL);
+       struct rtmdio_bus_priv *priv = bus->priv;
+       int combo_phy;
 
-       /* Enable PHY control via SoC */
-       sw_w32_mask(0, 1 << 15, RTMDIO_838X_SMI_GLB_CTRL);
+       /* Disable MAC polling for PHY config. It will be activated later in the DSA driver */
+       sw_w32(0, RTMDIO_838X_SMI_POLL_CTRL);
+
+       /*
+        * Control bits EX_PHY_MAN_xxx have an important effect on the detection of the media
+        * status (fibre/copper) of a PHY. Once activated, register MAC_LINK_MEDIA_STS can
+        * give the real media status (0=copper, 1=fibre). For now assume that if port 24 is
+        * PHY driven, it must be a combo PHY and media detection is needed.
+        */
+       combo_phy = priv->smi_bus[24] < 0 ? 0 : BIT(7);
+       sw_w32_mask(BIT(7), combo_phy, RTMDIO_838X_SMI_GLB_CTRL);
 
-       /* Probably should reset all PHYs here... */
        return 0;
 }