5.15-stable patches

added patches:
	drm-amd-display-avoid-a-null-pointer-dereference.patch
	drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch
	drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs.patch
	drm-amd-display-fix-dp-audio-dto1-clock-source-on-dce-6.patch
	drm-amd-display-fix-fractional-fb-divider-in-set_pixel_clock_v3.patch

diff --git a/queue-5.15/drm-amd-display-avoid-a-null-pointer-dereference.patch b/queue-5.15/drm-amd-display-avoid-a-null-pointer-dereference.patch
new file mode 100644 (file)
index 0000000..8244c3e
--- /dev/null
+++ b/queue-5.15/drm-amd-display-avoid-a-null-pointer-dereference.patch
@@ -0,0 +1,42 @@
+From 07b93a5704b0b72002f0c4bd1076214af67dc661 Mon Sep 17 00:00:00 2001
+From: Mario Limonciello <mario.limonciello@amd.com>
+Date: Thu, 24 Jul 2025 15:00:43 -0500
+Subject: drm/amd/display: Avoid a NULL pointer dereference
+
+From: Mario Limonciello <mario.limonciello@amd.com>
+
+commit 07b93a5704b0b72002f0c4bd1076214af67dc661 upstream.
+
+[WHY]
+Although unlikely drm_atomic_get_new_connector_state() or
+drm_atomic_get_old_connector_state() can return NULL.
+
+[HOW]
+Check returns before dereference.
+
+Cc: Mario Limonciello <mario.limonciello@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
+Signed-off-by: Alex Hung <alex.hung@amd.com>
+Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 1e5e8d672fec9f2ab352be121be971877bff2af9)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |    3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -7105,6 +7105,9 @@ amdgpu_dm_connector_atomic_check(struct
+       struct drm_crtc_state *new_crtc_state;
+       int ret;
+ 
++      if (WARN_ON(unlikely(!old_con_state || !new_con_state)))
++              return -EINVAL;
++
+       trace_amdgpu_dm_connector_atomic_check(new_con_state);
+ 
+       if (!crtc)

diff --git a/queue-5.15/drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch b/queue-5.15/drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch
new file mode 100644 (file)
index 0000000..14d2dac
--- /dev/null
+++ b/queue-5.15/drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch
@@ -0,0 +1,78 @@
+From 7d07140d37f792f01cfdb8ca9a6a792ab1d29126 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Timur=20Krist=C3=B3f?= <timur.kristof@gmail.com>
+Date: Thu, 31 Jul 2025 11:43:49 +0200
+Subject: drm/amd/display: Fill display clock and vblank time in dce110_fill_display_configs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Timur Kristóf <timur.kristof@gmail.com>
+
+commit 7d07140d37f792f01cfdb8ca9a6a792ab1d29126 upstream.
+
+Also needed by DCE 6.
+This way the code that gathers this info can be shared between
+different DCE versions and doesn't have to be repeated.
+
+Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com>
+Reviewed-by: Alex Hung <alex.hung@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 8107432dff37db26fcb641b6cebeae8981cd73a0)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c    |    2 --
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c |   10 +++-------
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c   |    2 --
+ 3 files changed, 3 insertions(+), 11 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+@@ -384,8 +384,6 @@ static void dce_pplib_apply_display_requ
+ {
+       struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
+ 
+-      pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
+-
+       dce110_fill_display_configs(context, pp_display_cfg);
+ 
+       if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+@@ -124,6 +124,9 @@ void dce110_fill_display_configs(
+       int j;
+       int num_cfgs = 0;
+ 
++      pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
++      pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
++      pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
+       pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator;
+ 
+       for (j = 0; j < context->stream_count; j++) {
+@@ -243,13 +246,6 @@ void dce11_pplib_apply_display_requireme
+       pp_display_cfg->min_engine_clock_deep_sleep_khz
+                       = context->bw_ctx.bw.dce.sclk_deep_sleep_khz;
+ 
+-      pp_display_cfg->avail_mclk_switch_time_us =
+-                                              dce110_get_min_vblank_time_us(context);
+-      /* TODO: dce11.2*/
+-      pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
+-
+-      pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
+-
+       dce110_fill_display_configs(context, pp_display_cfg);
+ 
+       if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
+@@ -100,8 +100,6 @@ static void dce60_pplib_apply_display_re
+ {
+       struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
+ 
+-      pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
+-
+       dce110_fill_display_configs(context, pp_display_cfg);
+ 
+       if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)

diff --git a/queue-5.15/drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs.patch b/queue-5.15/drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs.patch
new file mode 100644 (file)
index 0000000..770957d
--- /dev/null
+++ b/queue-5.15/drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs.patch
@@ -0,0 +1,84 @@
+From 669f73a26f6112eedbadac53a2f2707ac6d0b9c8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Timur=20Krist=C3=B3f?= <timur.kristof@gmail.com>
+Date: Thu, 31 Jul 2025 11:43:48 +0200
+Subject: drm/amd/display: Find first CRTC and its line time in dce110_fill_display_configs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Timur Kristóf <timur.kristof@gmail.com>
+
+commit 669f73a26f6112eedbadac53a2f2707ac6d0b9c8 upstream.
+
+dce110_fill_display_configs is shared between DCE 6-11, and
+finding the first CRTC and its line time is relevant to DCE 6 too.
+Move the code to find it from DCE 11 specific code.
+
+Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com>
+Reviewed-by: Alex Hung <alex.hung@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 4ab09785f8d5d03df052827af073d5c508ff5f63)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c |   30 ++++++----
+ 1 file changed, 20 insertions(+), 10 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+@@ -120,9 +120,12 @@ void dce110_fill_display_configs(
+       const struct dc_state *context,
+       struct dm_pp_display_configuration *pp_display_cfg)
+ {
++      struct dc *dc = context->clk_mgr->ctx->dc;
+       int j;
+       int num_cfgs = 0;
+ 
++      pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator;
++
+       for (j = 0; j < context->stream_count; j++) {
+               int k;
+ 
+@@ -164,6 +167,23 @@ void dce110_fill_display_configs(
+               cfg->v_refresh /= stream->timing.h_total;
+               cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
+                                                       / stream->timing.v_total;
++
++              /* Find first CRTC index and calculate its line time.
++               * This is necessary for DPM on SI GPUs.
++               */
++              if (cfg->pipe_idx < pp_display_cfg->crtc_index) {
++                      const struct dc_crtc_timing *timing =
++                              &context->streams[0]->timing;
++
++                      pp_display_cfg->crtc_index = cfg->pipe_idx;
++                      pp_display_cfg->line_time_in_us =
++                              timing->h_total * 10000 / timing->pix_clk_100hz;
++              }
++      }
++
++      if (!num_cfgs) {
++              pp_display_cfg->crtc_index = 0;
++              pp_display_cfg->line_time_in_us = 0;
+       }
+ 
+       pp_display_cfg->display_count = num_cfgs;
+@@ -232,16 +252,6 @@ void dce11_pplib_apply_display_requireme
+ 
+       dce110_fill_display_configs(context, pp_display_cfg);
+ 
+-      /* TODO: is this still applicable?*/
+-      if (pp_display_cfg->display_count == 1) {
+-              const struct dc_crtc_timing *timing =
+-                      &context->streams[0]->timing;
+-
+-              pp_display_cfg->crtc_index =
+-                      pp_display_cfg->disp_configs[0].pipe_idx;
+-              pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz;
+-      }
+-
+       if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
+               dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
+ }

diff --git a/queue-5.15/drm-amd-display-fix-dp-audio-dto1-clock-source-on-dce-6.patch b/queue-5.15/drm-amd-display-fix-dp-audio-dto1-clock-source-on-dce-6.patch
new file mode 100644 (file)
index 0000000..b74556a
--- /dev/null
+++ b/queue-5.15/drm-amd-display-fix-dp-audio-dto1-clock-source-on-dce-6.patch
@@ -0,0 +1,91 @@
+From 297a4833a68aac3316eb808b4123eb016ef242d7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Timur=20Krist=C3=B3f?= <timur.kristof@gmail.com>
+Date: Sat, 2 Aug 2025 17:51:53 +0200
+Subject: drm/amd/display: Fix DP audio DTO1 clock source on DCE 6.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Timur Kristóf <timur.kristof@gmail.com>
+
+commit 297a4833a68aac3316eb808b4123eb016ef242d7 upstream.
+
+On DCE 6, DP audio was not working. However, it worked when an
+HDMI monitor was also plugged in.
+
+Looking at dce_aud_wall_dto_setup it seems that the main
+difference is that we use DTO1 when only DP is plugged in.
+
+When programming DTO1, it uses audio_dto_source_clock_in_khz
+which is set from get_dp_ref_freq_khz
+
+The dce60_get_dp_ref_freq_khz implementation looks incorrect,
+because DENTIST_DISPCLK_CNTL seems to be always zero on DCE 6,
+so it isn't usable.
+I compared dce60_get_dp_ref_freq_khz to the legacy display code,
+specifically dce_v6_0_audio_set_dto, and it turns out that in
+case of DCE 6, it needs to use the display clock. With that,
+DP audio started working on Pitcairn, Oland and Cape Verde.
+
+However, it still didn't work on Tahiti. Despite having the
+same DCE version, Tahiti seems to have a different audio device.
+After some trial and error I realized that it works with the
+default display clock as reported by the VBIOS, not the current
+display clock.
+
+The patch was tested on all four SI GPUs:
+
+* Pitcairn (DCE 6.0)
+* Oland (DCE 6.4)
+* Cape Verde (DCE 6.0)
+* Tahiti (DCE 6.0 but different)
+
+The testing was done on Samsung Odyssey G7 LS28BG700EPXEN on
+each of the above GPUs, at the following settings:
+
+* 4K 60 Hz
+* 1080p 60 Hz
+* 1080p 144 Hz
+
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com>
+Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 645cc7863da5de700547d236697dffd6760cf051)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c |   21 +++--------
+ 1 file changed, 6 insertions(+), 15 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
+@@ -83,22 +83,13 @@ static const struct state_dependent_cloc
+ static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
+ {
+       struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+-      int dprefclk_wdivider;
+-      int dp_ref_clk_khz;
+-      int target_div;
++      struct dc_context *ctx = clk_mgr_base->ctx;
++      int dp_ref_clk_khz = 0;
+ 
+-      /* DCE6 has no DPREFCLK_CNTL to read DP Reference Clock source */
+-
+-      /* Read the mmDENTIST_DISPCLK_CNTL to get the currently
+-       * programmed DID DENTIST_DPREFCLK_WDIVIDER*/
+-      REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
+-
+-      /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
+-      target_div = dentist_get_divider_from_did(dprefclk_wdivider);
+-
+-      /* Calculate the current DFS clock, in kHz.*/
+-      dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+-              * clk_mgr->base.dentist_vco_freq_khz) / target_div;
++      if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev))
++              dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency;
++      else
++              dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz;
+ 
+       return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
+ }

diff --git a/queue-5.15/drm-amd-display-fix-fractional-fb-divider-in-set_pixel_clock_v3.patch b/queue-5.15/drm-amd-display-fix-fractional-fb-divider-in-set_pixel_clock_v3.patch
new file mode 100644 (file)
index 0000000..46f8717
--- /dev/null
+++ b/queue-5.15/drm-amd-display-fix-fractional-fb-divider-in-set_pixel_clock_v3.patch
@@ -0,0 +1,53 @@
+From 10507478468f165ea681605d133991ed05cdff62 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Timur=20Krist=C3=B3f?= <timur.kristof@gmail.com>
+Date: Thu, 31 Jul 2025 11:43:52 +0200
+Subject: drm/amd/display: Fix fractional fb divider in set_pixel_clock_v3
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Timur Kristóf <timur.kristof@gmail.com>
+
+commit 10507478468f165ea681605d133991ed05cdff62 upstream.
+
+For later VBIOS versions, the fractional feedback divider is
+calculated as the remainder of dividing the feedback divider by
+a factor, which is set to 1000000. For reference, see:
+- calculate_fb_and_fractional_fb_divider
+- calc_pll_max_vco_construct
+
+However, in case of old VBIOS versions that have
+set_pixel_clock_v3, they only have 1 byte available for the
+fractional feedback divider, and it's expected to be set to the
+remainder from dividing the feedback divider by 10.
+For reference see the legacy display code:
+- amdgpu_pll_compute
+- amdgpu_atombios_crtc_program_pll
+
+This commit fixes set_pixel_clock_v3 by dividing the fractional
+feedback divider passed to the function by 100000.
+
+Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
+Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com>
+Reviewed-by: Alex Hung <alex.hung@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 027e7acc7e17802ebf28e1edb88a404836ad50d6)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/bios/command_table.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+@@ -992,7 +992,7 @@ static enum bp_result set_pixel_clock_v3
+       allocation.sPCLKInput.usFbDiv =
+                       cpu_to_le16((uint16_t)bp_params->feedback_divider);
+       allocation.sPCLKInput.ucFracFbDiv =
+-                      (uint8_t)bp_params->fractional_feedback_divider;
++                      (uint8_t)(bp_params->fractional_feedback_divider / 100000);
+       allocation.sPCLKInput.ucPostDiv =
+                       (uint8_t)bp_params->pixel_clock_post_divider;
+ 

diff --git a/queue-5.15/series b/queue-5.15/series
index 56a01c45b9f9139dcd704bef7e8d39a3e12f05ea..973391eadcf7e6f17b8a6c87ca6d7c1ebbd208fc 100644 (file)
--- a/queue-5.15/series
+++ b/queue-5.15/series
@@ -566,3 +566,8 @@ mmc-sdhci-pci-gli-gl9763e-rename-the-gli_set_gl9763e-for-consistency.patch
 squashfs-fix-memory-leak-in-squashfs_fill_super.patch
 mm-debug_vm_pgtable-clear-page-table-entries-at-destroy_args.patch
 alsa-hda-realtek-add-support-for-hp-elitebook-x360-830-g6-and-elitebook-830-g6.patch
+drm-amd-display-avoid-a-null-pointer-dereference.patch
+drm-amd-display-fix-fractional-fb-divider-in-set_pixel_clock_v3.patch
+drm-amd-display-fix-dp-audio-dto1-clock-source-on-dce-6.patch
+drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs.patch
+drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch