From: Julian Seward Date: Fri, 30 Jul 2004 16:17:28 +0000 (+0000) Subject: Fix up generation of shldl/shldr instructions, and thereby X-Git-Tag: svn/VALGRIND_3_0_1^2~1171 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=001469740ecb77c4f82b48119adb80b894f46f47;p=thirdparty%2Fvalgrind.git Fix up generation of shldl/shldr instructions, and thereby unbreak implementation of Shr64 for x86 targets. git-svn-id: svn://svn.valgrind.org/vex/trunk@163 --- diff --git a/VEX/priv/host-x86/hdefs.c b/VEX/priv/host-x86/hdefs.c index d89c47ffd2..fe0a6010e0 100644 --- a/VEX/priv/host-x86/hdefs.c +++ b/VEX/priv/host-x86/hdefs.c @@ -454,13 +454,13 @@ X86Instr* X86Instr_Div ( Bool syned, X86ScalarSz ssz, X86RM* src ) { i->Xin.Div.src = src; return i; } -X86Instr* X86Instr_Sh3232 ( X86ShiftOp op, UInt amt, HReg rHi, HReg rLo ) { +X86Instr* X86Instr_Sh3232 ( X86ShiftOp op, UInt amt, HReg src, HReg dst ) { X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); i->tag = Xin_Sh3232; i->Xin.Sh3232.op = op; i->Xin.Sh3232.amt = amt; - i->Xin.Sh3232.rHi = rHi; - i->Xin.Sh3232.rLo = rLo; + i->Xin.Sh3232.src = src; + i->Xin.Sh3232.dst = dst; vassert(op == Xsh_SHL || op == Xsh_SHR); return i; } @@ -567,9 +567,9 @@ void ppX86Instr ( X86Instr* i ) { vex_printf(" %%cl,"); else vex_printf(" $%d,", i->Xin.Sh3232.amt); - ppHRegX86(i->Xin.Sh3232.rLo); + ppHRegX86(i->Xin.Sh3232.src); vex_printf(","); - ppHRegX86(i->Xin.Sh3232.rHi); + ppHRegX86(i->Xin.Sh3232.dst); return; case Xin_Push: vex_printf("pushl "); @@ -667,8 +667,8 @@ void getRegUsage_X86Instr (HRegUsage* u, X86Instr* i) addHRegUse(u, HRmModify, hregX86_EDX()); return; case Xin_Sh3232: - addHRegUse(u, HRmRead, i->Xin.Sh3232.rLo); - addHRegUse(u, HRmModify, i->Xin.Sh3232.rHi); + addHRegUse(u, HRmRead, i->Xin.Sh3232.src); + addHRegUse(u, HRmModify, i->Xin.Sh3232.dst); if (i->Xin.Sh3232.amt == 0) addHRegUse(u, HRmRead, hregX86_ECX()); return; @@ -743,8 +743,8 @@ void mapRegs_X86Instr (HRegRemap* m, X86Instr* i) mapRegs_X86RM(m, i->Xin.Div.src); return; case Xin_Sh3232: - mapReg(m, &i->Xin.Sh3232.rLo); - mapReg(m, &i->Xin.Sh3232.rHi); + mapReg(m, &i->Xin.Sh3232.src); + mapReg(m, &i->Xin.Sh3232.dst); return; case Xin_Push: mapRegs_X86RMI(m, i->Xin.Push.src); @@ -1208,11 +1208,10 @@ Int emit_X86Instr ( UChar* buf, Int nbuf, X86Instr* i ) *p++ = 0x0F; if (i->Xin.Sh3232.op == Xsh_SHL) { *p++ = 0xA5; - p = doAMode_R(p, i->Xin.Sh3232.rLo, i->Xin.Sh3232.rHi); } else { *p++ = 0xAD; - p = doAMode_R(p, i->Xin.Sh3232.rHi, i->Xin.Sh3232.rLo); } + p = doAMode_R(p, i->Xin.Sh3232.src, i->Xin.Sh3232.dst); goto done; } break; diff --git a/VEX/priv/host-x86/hdefs.h b/VEX/priv/host-x86/hdefs.h index 76924117c0..f2b6c2cdd1 100644 --- a/VEX/priv/host-x86/hdefs.h +++ b/VEX/priv/host-x86/hdefs.h @@ -308,8 +308,8 @@ typedef struct { X86ShiftOp op; UInt amt; /* shift amount, or 0 means %cl */ - HReg rHi; - HReg rLo; + HReg src; + HReg dst; } Sh3232; struct { X86RMI* src; @@ -359,7 +359,7 @@ extern X86Instr* X86Instr_Sh32 ( X86ShiftOp, UInt, X86RM* ); extern X86Instr* X86Instr_Test32 ( X86RI* src, X86RM* dst ); extern X86Instr* X86Instr_MulL ( Bool syned, X86ScalarSz, X86RM* ); extern X86Instr* X86Instr_Div ( Bool syned, X86ScalarSz, X86RM* ); -extern X86Instr* X86Instr_Sh3232 ( X86ShiftOp, UInt amt, HReg rHi, HReg rLo ); +extern X86Instr* X86Instr_Sh3232 ( X86ShiftOp, UInt amt, HReg src, HReg dst ); extern X86Instr* X86Instr_Push ( X86RMI* ); extern X86Instr* X86Instr_Call ( HReg ); extern X86Instr* X86Instr_Goto ( IRJumpKind, X86CondCode cond, X86RI* dst ); diff --git a/VEX/priv/host-x86/isel.c b/VEX/priv/host-x86/isel.c index 08855c3f0f..1084b1f4d6 100644 --- a/VEX/priv/host-x86/isel.c +++ b/VEX/priv/host-x86/isel.c @@ -867,7 +867,7 @@ static void iselIntExpr64 ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e ) addInstr(env, mk_MOVsd_RR(sLo, tLo)); /* Ok. Now shift amt is in %ecx, and value is in tHi/tLo and those regs are legitimately modifiable. */ - addInstr(env, X86Instr_Sh3232(Xsh_SHL, 0/*%cl*/, tHi, tLo)); + addInstr(env, X86Instr_Sh3232(Xsh_SHL, 0/*%cl*/, tLo, tHi)); addInstr(env, X86Instr_Sh32(Xsh_SHL, 0/*%cl*/, X86RM_Reg(tLo))); addInstr(env, X86Instr_Test32(X86RI_Imm(32), X86RM_Reg(hregX86_ECX()))); addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(tLo), tHi)); @@ -910,7 +910,7 @@ static void iselIntExpr64 ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e ) addInstr(env, mk_MOVsd_RR(sLo, tLo)); /* Ok. Now shift amt is in %ecx, and value is in tHi/tLo and those regs are legitimately modifiable. */ - addInstr(env, X86Instr_Sh3232(Xsh_SHR, 0/*%cl*/, tLo, tHi)); + addInstr(env, X86Instr_Sh3232(Xsh_SHR, 0/*%cl*/, tHi, tLo)); addInstr(env, X86Instr_Sh32(Xsh_SHR, 0/*%cl*/, X86RM_Reg(tHi))); addInstr(env, X86Instr_Test32(X86RI_Imm(32), X86RM_Reg(hregX86_ECX()))); addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(tHi), tLo));