From: Alex Deucher Date: Fri, 10 Oct 2025 20:47:02 +0000 (-0400) Subject: drm/amdgpu: Update AMDGPU_INFO_UQ_FW_AREAS query for sdma X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0030595c3e8b48b32a12b8354ce9dbe00efd632f;p=thirdparty%2Fkernel%2Flinux.git drm/amdgpu: Update AMDGPU_INFO_UQ_FW_AREAS query for sdma Add a query for sdma queues. Userspace can use this to query the size of the CSA buffers for sdma user queues. Proposed userspace: https://gitlab.freedesktop.org/yogeshmohan/mesa/-/commits/userq_query Reviewed-by: Prike Liang Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index b02da84ab99d..36fdd1af9d6b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -409,6 +409,24 @@ static int amdgpu_userq_metadata_info_compute(struct amdgpu_device *adev, return ret; } +static int amdgpu_userq_metadata_info_sdma(struct amdgpu_device *adev, + struct drm_amdgpu_info *info, + struct drm_amdgpu_info_uq_metadata_sdma *meta) +{ + int ret = -EOPNOTSUPP; + + if (adev->sdma.get_csa_info) { + struct amdgpu_sdma_csa_info csa = {}; + + adev->sdma.get_csa_info(adev, &csa); + meta->csa_size = csa.size; + meta->csa_alignment = csa.alignment; + ret = 0; + } + + return ret; +} + static int amdgpu_hw_ip_info(struct amdgpu_device *adev, struct drm_amdgpu_info *info, struct drm_amdgpu_info_hw_ip *result) @@ -1386,6 +1404,14 @@ out: if (ret) return ret; + ret = copy_to_user(out, &meta_info, + min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; + return 0; + case AMDGPU_HW_IP_DMA: + ret = amdgpu_userq_metadata_info_sdma(adev, info, &meta_info.sdma); + if (ret) + return ret; + ret = copy_to_user(out, &meta_info, min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; return 0; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 138d9ae1aa48..f902add31fc6 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -1637,10 +1637,18 @@ struct drm_amdgpu_info_uq_metadata_compute { __u32 eop_alignment; }; +struct drm_amdgpu_info_uq_metadata_sdma { + /* context save area size for sdma6 */ + __u32 csa_size; + /* context save area base virtual alignment for sdma6 */ + __u32 csa_alignment; +}; + struct drm_amdgpu_info_uq_metadata { union { struct drm_amdgpu_info_uq_metadata_gfx gfx; struct drm_amdgpu_info_uq_metadata_compute compute; + struct drm_amdgpu_info_uq_metadata_sdma sdma; }; };