From: Michal Piekos Date: Wed, 6 May 2026 15:10:28 +0000 (+0200) Subject: riscv: dts: allwinner: d1s-t113: add hstimer node X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=003ff312269cc9defdd6b12462b1e89f4c9423d7;p=thirdparty%2Flinux.git riscv: dts: allwinner: d1s-t113: add hstimer node Describe high speed timer block on Allwinner D1S-T113. Tested on LCPI-PC-T113/F113: - hstimer is registered as clocksource - switching clocksource at runtime works - after rating increase hstimer operates as a broadcast clockevent device Signed-off-by: Michal Piekos Reviewed-by: Chen-Yu Tsai Link: https://patch.msgid.link/20260506-h616-t113s-hstimer-v4-3-591d425863d6@mmpsystems.pl [wens@kernel.org: change subject prefix from "arm" to "riscv"] [wens@kernel.org: fix interrupt representation] Signed-off-by: Chen-Yu Tsai --- diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 82cc85acccb13..a810ad3eb2a2b 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -295,6 +295,15 @@ clocks = <&dcxo>; }; + hstimer@3008000 { + compatible = "allwinner,sun20i-d1-hstimer"; + reg = <0x03008000 0x1000>; + interrupts = , + ; + clocks = <&ccu CLK_BUS_HSTIMER>; + resets = <&ccu RST_BUS_HSTIMER>; + }; + wdt: watchdog@20500a0 { compatible = "allwinner,sun20i-d1-wdt-reset", "allwinner,sun20i-d1-wdt";