From: Zephyr Li <fritchleybohrer@gmail.com>
Date: Fri, 12 Jun 2026 01:36:17 +0000 (+0800)
Subject: lscpu: add RISC-V MMU column support
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=008f428410a0065e807e3424d402d238453d92e2;p=thirdparty%2Futil-linux.git

lscpu: add RISC-V MMU column support

Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>
---

diff --git a/bash-completion/lscpu b/bash-completion/lscpu
index 8d54df188..b4b0803d0 100644
--- a/bash-completion/lscpu
+++ b/bash-completion/lscpu
@@ -12,7 +12,7 @@ _lscpu_module()
 			prefix="${cur%$realcur}"
 			OPTS_ALL="CPU CORE SOCKET NODE
 				BOOK DRAWER CACHE POLARIZATION ADDRESS
-				CONFIGURED ONLINE MICROCODE MAXMHZ MINMHZ"
+				CONFIGURED ONLINE MICROCODE MMU MAXMHZ MINMHZ"
 			for WORD in $OPTS_ALL; do
 				if ! [[ $prefix == *"$WORD"* ]]; then
 					OPTS="$WORD ${OPTS:-""}"
diff --git a/sys-utils/lscpu.c b/sys-utils/lscpu.c
index 66ad03f4b..5257b9b92 100644
--- a/sys-utils/lscpu.c
+++ b/sys-utils/lscpu.c
@@ -101,6 +101,7 @@ enum {
 	COL_CPU_CONFIGURED,
 	COL_CPU_ONLINE,
 	COL_CPU_MICROCODE,
+	COL_CPU_MMU,
 	COL_CPU_MHZ,
 	COL_CPU_SCALMHZ,
 	COL_CPU_MAXMHZ,
@@ -150,6 +151,7 @@ static struct lscpu_coldesc coldescs_cpu[] =
 	[COL_CPU_CONFIGURED]   = { "CONFIGURED", N_("shows if the hypervisor has allocated the CPU"), 0, 0, SCOLS_JSON_BOOLEAN_OPTIONAL },
 	[COL_CPU_ONLINE]       = { "ONLINE", N_("shows if Linux currently makes use of the CPU"), SCOLS_FL_RIGHT, 0, SCOLS_JSON_BOOLEAN_OPTIONAL },
 	[COL_CPU_MICROCODE]    = { "MICROCODE", N_("shows the loaded CPU microcode version"), 0, 0, SCOLS_JSON_STRING },
+	[COL_CPU_MMU]          = { "MMU", N_("shows the RISC-V MMU mode"), 0, 0, SCOLS_JSON_STRING },
 	[COL_CPU_MHZ]          = { "MHZ", N_("shows the current MHz of the CPU"), SCOLS_FL_RIGHT, 0, SCOLS_JSON_NUMBER },
 	[COL_CPU_SCALMHZ]      = { "SCALMHZ%", N_("shows scaling percentage of the CPU frequency"), SCOLS_FL_RIGHT, SCOLS_JSON_NUMBER },
 	[COL_CPU_MAXMHZ]       = { "MAXMHZ", N_("shows the maximum MHz of the CPU"), SCOLS_FL_RIGHT, 0, SCOLS_JSON_NUMBER },
@@ -440,6 +442,10 @@ static char *get_cell_data(
 		if (cpu->type && cpu->type->microcode)
 			xstrncpy(buf, cpu->type->microcode, bufsz);
 		break;
+	case COL_CPU_MMU:
+		if (cpu->type && cpu->type->mmu)
+			xstrncpy(buf, cpu->type->mmu, bufsz);
+		break;
 	case COL_CPU_MHZ:
 		if (cpu->mhz_cur_freq)
 			snprintf(buf, bufsz, "%.4f", cpu->mhz_cur_freq);
diff --git a/tests/expected/lscpu/lscpu-rv64-linux b/tests/expected/lscpu/lscpu-rv64-linux
index fbfea0b4f..7b8142f35 100644
--- a/tests/expected/lscpu/lscpu-rv64-linux
+++ b/tests/expected/lscpu/lscpu-rv64-linux
@@ -5,6 +5,7 @@ Thread(s) per core:  2
 Core(s) per socket:  1
 Socket(s):           1
 ISA:                 rv64imafdc
+MMU:                 sv39
 L1d cache:           64 KiB (2 instances)
 L1i cache:           64 KiB (2 instances)
 L2 cache:            2 MiB (1 instance)
diff --git a/tests/expected/lscpu/lscpu-rv64-milkvpioneer b/tests/expected/lscpu/lscpu-rv64-milkvpioneer
index 69a574b97..516c4be93 100644
--- a/tests/expected/lscpu/lscpu-rv64-milkvpioneer
+++ b/tests/expected/lscpu/lscpu-rv64-milkvpioneer
@@ -8,6 +8,7 @@ Thread(s) per core:  1
 Core(s) per socket:  64
 Socket(s):           1
 ISA:                 rv64imafdcv
+MMU:                 sv39
 NUMA node(s):        4
 NUMA node0 CPU(s):   0-7,16-23
 NUMA node1 CPU(s):   8-15,24-31
diff --git a/tests/expected/lscpu/lscpu-rv64-visionfive2 b/tests/expected/lscpu/lscpu-rv64-visionfive2
index cd87ba57b..762d7216b 100644
--- a/tests/expected/lscpu/lscpu-rv64-visionfive2
+++ b/tests/expected/lscpu/lscpu-rv64-visionfive2
@@ -9,6 +9,7 @@ Thread(s) per core:  1
 Core(s) per socket:  4
 Socket(s):           1
 ISA:                 rv64imafdc zba zbb zicntr zicsr zifencei zihpm
+MMU:                 sv39
 L1d cache:           128 KiB (4 instances)
 L1i cache:           128 KiB (4 instances)
 L2 cache:            2 MiB (1 instance)