From: Julian Seward Date: Thu, 3 Apr 2014 23:01:24 +0000 (+0000) Subject: Add tests for some variants of LD{1,2}/ST{1,2} that load or X-Git-Tag: svn/VALGRIND_3_10_0~547 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=00cbf4454fd563e69f0ce3ecdbf8e0332c38cc42;p=thirdparty%2Fvalgrind.git Add tests for some variants of LD{1,2}/ST{1,2} that load or store two registers. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13889 --- diff --git a/none/tests/arm64/test_arm64_int.c b/none/tests/arm64/test_arm64_int.c index 8fbc4bc17a..986b12d306 100644 --- a/none/tests/arm64/test_arm64_int.c +++ b/none/tests/arm64/test_arm64_int.c @@ -10794,18 +10794,18 @@ static void show_block_xor ( UChar* block1, UChar* block2, Int n ) // Out: memory area, xferred vec regs, xferred int regs, addr reg1, addr reg2 // // INSN may mention the following regs as containing load/store data: -// x13 x23 v17 v31 +// x13 x23 v17 v18 // and // x5 as containing the base address // x6 as containing an offset, if required -// A memory area is filled with random data, and x13, x23, v17 and v31 +// A memory area is filled with random data, and x13, x23, v17 and v18 // are loaded with random data too. INSN is then executed, with // x5 set to the middle of the memory area + AREG1OFF, and x6 set to AREG2VAL. // // What is printed out: the XOR of the old and new versions of the // following: // the memory area -// x13 x23 v17 v31 +// x13 x23 v17 v18 // and the new-old values of these // x5 x6 // If the insn modifies its base register then the x5 version will @@ -10817,7 +10817,7 @@ static void show_block_xor ( UChar* block1, UChar* block2, Int n ) UChar* area = memalign16(N); \ UChar area2[N]; \ for (i = 0; i < N; i++) area[i] = area2[i] = randUChar(); \ - ULong block[8]; /* x13 x23 v17.d[0] v17.d[1] v31.d[0] v31.d[1] x5 x6 */ \ + ULong block[8]; /* x13 x23 v17.d[0] v17.d[1] v18.d[0] v18.d[1] x5 x6 */ \ for (i = 0; i < 6; i++) block[i] = randULong(); \ block[6] = (ULong)(&area[128]) + (Long)(Int)AREG1OFF; \ block[7] = (Long)AREG2VAL; \ @@ -10827,17 +10827,17 @@ static void show_block_xor ( UChar* block1, UChar* block2, Int n ) "ldr x13, [%0, #0] ; " \ "ldr x23, [%0, #8] ; " \ "ldr q17, [%0, #16] ; " \ - "ldr q31, [%0, #32] ; " \ + "ldr q18, [%0, #32] ; " \ "ldr x5, [%0, #48] ; " \ "ldr x6, [%0, #56] ; " \ INSN " ; " \ "str x13, [%0, #0] ; " \ "str x23, [%0, #8] ; " \ "str q17, [%0, #16] ; " \ - "str q31, [%0, #32] ; " \ + "str q18, [%0, #32] ; " \ "str x5, [%0, #48] ; " \ "str x6, [%0, #56] ; " \ - : : "r"(&block[0]) : "x5", "x6", "x13","x23","v17","v31","memory","cc" \ + : : "r"(&block[0]) : "x5", "x6", "x13","x23","v17","v18","memory","cc" \ ); \ printf("%s with x5 = middle_of_block+%lld, x6=%lld\n", \ INSN, (Long)AREG1OFF, (Long)AREG2VAL); \ @@ -10846,8 +10846,8 @@ static void show_block_xor ( UChar* block1, UChar* block2, Int n ) printf(" %016llx x23 (xfer intreg #2)\n", block[1] ^ block2[1]); \ printf(" %016llx v17.d[0] (xfer vecreg #1)\n", block[2] ^ block2[2]); \ printf(" %016llx v17.d[1] (xfer vecreg #1)\n", block[3] ^ block2[3]); \ - printf(" %016llx v31.d[0] (xfer vecreg #2)\n", block[4] ^ block2[4]); \ - printf(" %016llx v31.d[1] (xfer vecreg #2)\n", block[5] ^ block2[5]); \ + printf(" %016llx v18.d[0] (xfer vecreg #2)\n", block[4] ^ block2[4]); \ + printf(" %016llx v18.d[1] (xfer vecreg #2)\n", block[5] ^ block2[5]); \ printf(" %16lld x5 (base reg)\n", block[6] - block2[6]); \ printf(" %16lld x6 (index reg)\n", block[7] - block2[7]); \ printf("\n"); \ @@ -10982,29 +10982,29 @@ MEM_TEST("ldrsb w13, [x5, #-56]", -16, 4); //////////////////////////////////////////////////////////////// printf("LDP,STP (immediate, simm7) (FP&VEC)\n"); -MEM_TEST("stp q17, q31, [x5, 32]", -16, 4); -MEM_TEST("stp q17, q31, [x5, 32]!", -16, 4); -MEM_TEST("stp q17, q31, [x5], 32", -16, 4); +MEM_TEST("stp q17, q18, [x5, 32]", -16, 4); +MEM_TEST("stp q17, q18, [x5, 32]!", -16, 4); +MEM_TEST("stp q17, q18, [x5], 32", -16, 4); -MEM_TEST("stp d17, d31, [x5, 32]", -16, 4); -MEM_TEST("stp d17, d31, [x5, 32]!", -16, 4); -MEM_TEST("stp d17, d31, [x5], 32", -16, 4); +MEM_TEST("stp d17, d18, [x5, 32]", -16, 4); +MEM_TEST("stp d17, d18, [x5, 32]!", -16, 4); +MEM_TEST("stp d17, d18, [x5], 32", -16, 4); -//MEM_TEST("stp s17, s31, [x5, 32]", -16, 4); -//MEM_TEST("stp s17, s31, [x5, 32]!", -16, 4); -//MEM_TEST("stp s17, s31, [x5], 32", -16, 4); +//MEM_TEST("stp s17, s18, [x5, 32]", -16, 4); +//MEM_TEST("stp s17, s18, [x5, 32]!", -16, 4); +//MEM_TEST("stp s17, s18, [x5], 32", -16, 4); -MEM_TEST("ldp q17, q31, [x5, 32]", -16, 4); -MEM_TEST("ldp q17, q31, [x5, 32]!", -16, 4); -MEM_TEST("ldp q17, q31, [x5], 32", -16, 4); +MEM_TEST("ldp q17, q18, [x5, 32]", -16, 4); +MEM_TEST("ldp q17, q18, [x5, 32]!", -16, 4); +MEM_TEST("ldp q17, q18, [x5], 32", -16, 4); -MEM_TEST("ldp d17, d31, [x5, 32]", -16, 4); -MEM_TEST("ldp d17, d31, [x5, 32]!", -16, 4); -MEM_TEST("ldp d17, d31, [x5], 32", -16, 4); +MEM_TEST("ldp d17, d18, [x5, 32]", -16, 4); +MEM_TEST("ldp d17, d18, [x5, 32]!", -16, 4); +MEM_TEST("ldp d17, d18, [x5], 32", -16, 4); -//MEM_TEST("ldp s17, s31, [x5, 32]", -16, 4); -//MEM_TEST("ldp s17, s31, [x5, 32]!", -16, 4); -//MEM_TEST("ldp s17, s31, [x5], 32", -16, 4); +//MEM_TEST("ldp s17, s18, [x5, 32]", -16, 4); +//MEM_TEST("ldp s17, s18, [x5, 32]!", -16, 4); +//MEM_TEST("ldp s17, s18, [x5], 32", -16, 4); //////////////////////////////////////////////////////////////// printf("{LD,ST}R (vector register)\n"); @@ -11198,19 +11198,36 @@ MEM_TEST("st1 {v17.2d}, [x5], #16", 3, 0) MEM_TEST("st1 {v17.4s}, [x5], #16", 5, 0) MEM_TEST("st1 {v17.8h}, [x5], #16", 7, 0) MEM_TEST("st1 {v17.16b}, [x5], #16", 13, 0) -//MEM_TEST("st1 {v17.1d}, [x5], #8", 3, 0) +MEM_TEST("st1 {v17.1d}, [x5], #8", 3, 0) MEM_TEST("st1 {v17.2s}, [x5], #8", 5, 0) MEM_TEST("st1 {v17.4h}, [x5], #8", 7, 0) -//MEM_TEST("st1 {v17.8b}, [x5], #8", 13, 0) +MEM_TEST("st1 {v17.8b}, [x5], #8", 13, 0) MEM_TEST("ld1 {v17.2d}, [x5], #16", 3, 0) MEM_TEST("ld1 {v17.4s}, [x5], #16", 5, 0) MEM_TEST("ld1 {v17.8h}, [x5], #16", 7, 0) MEM_TEST("ld1 {v17.16b}, [x5], #16", 13, 0) -//MEM_TEST("ld1 {v17.1d}, [x5], #8", 3, 0) -//MEM_TEST("ld1 {v17.2s}, [x5], #8", 5, 0) -//MEM_TEST("ld1 {v17.4h}, [x5], #8", 7, 0) -//MEM_TEST("ld1 {v17.8b}, [x5], #8", 13, 0) +MEM_TEST("ld1 {v17.1d}, [x5], #8", 3, 0) +MEM_TEST("ld1 {v17.2s}, [x5], #8", 5, 0) +MEM_TEST("ld1 {v17.4h}, [x5], #8", 7, 0) +MEM_TEST("ld1 {v17.8b}, [x5], #8", 13, 0) + +//////////////////////////////////////////////////////////////// +printf("LD2/ST2 (multiple structures, post index) (VERY INCOMPLETE)\n"); + +MEM_TEST("ld2 {v17.2d, v18.2d}, [x5], #32", 3, 0) +MEM_TEST("st2 {v17.2d, v18.2d}, [x5], #32", 7, 0) + +MEM_TEST("ld2 {v17.4s, v18.4s}, [x5], #32", 13, 0) +MEM_TEST("st2 {v17.4s, v18.4s}, [x5], #32", 17, 0) + + +//////////////////////////////////////////////////////////////// +printf("LD1/ST1 (multiple structures, no offset) (VERY INCOMPLETE)\n"); + +MEM_TEST("ld1 {v17.16b, v18.16b}, [x5]", 3, 0) +MEM_TEST("st1 {v17.16b, v18.16b}, [x5]", 7, 0) + } /* end of test_memory2() */ @@ -11225,6 +11242,6 @@ int main ( void ) { if (1) test_arith(); if (1) test_memory(); - test_memory2(); + if (1) test_memory2(); return 0; }