From: Sasha Levin Date: Mon, 11 Jul 2022 05:36:09 +0000 (-0400) Subject: Fixes for 5.15 X-Git-Tag: v4.9.323~25 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=015f9e4c7482faceef28dafbf345eb8e5f0ada56;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 5.15 Signed-off-by: Sasha Levin --- diff --git a/queue-5.15/arm-at91-fix-soc-detection-for-sam9x60-sips.patch b/queue-5.15/arm-at91-fix-soc-detection-for-sam9x60-sips.patch new file mode 100644 index 00000000000..e339df5a735 --- /dev/null +++ b/queue-5.15/arm-at91-fix-soc-detection-for-sam9x60-sips.patch @@ -0,0 +1,51 @@ +From 6f3f7451e552c0d1d2fe5d1bf32440337d4f993b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 16 Jun 2022 11:13:44 +0300 +Subject: ARM: at91: fix soc detection for SAM9X60 SiPs + +From: Mihai Sain + +[ Upstream commit 35074df65a8d8c5328a83e2eea948f7bbc8e6e08 ] + +Fix SoC detection for SAM9X60 SiPs: +SAM9X60D5M +SAM9X60D1G +SAM9X60D6K + +Fixes: af3a10513cd6 ("drivers: soc: atmel: add per soc id and version match masks") +Signed-off-by: Mihai Sain +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20220616081344.1978664-1-claudiu.beznea@microchip.com +Signed-off-by: Sasha Levin +--- + drivers/soc/atmel/soc.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c +index a490ad7e090f..9e3d37011447 100644 +--- a/drivers/soc/atmel/soc.c ++++ b/drivers/soc/atmel/soc.c +@@ -91,14 +91,14 @@ static const struct at91_soc socs[] __initconst = { + AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, + "sam9x60", "sam9x60"), +- AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH, +- AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, ++ AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAM9X60_D5M_EXID_MATCH, + "sam9x60 64MiB DDR2 SiP", "sam9x60"), +- AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH, +- AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, ++ AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAM9X60_D1G_EXID_MATCH, + "sam9x60 128MiB DDR2 SiP", "sam9x60"), +- AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH, +- AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, ++ AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK, ++ AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH, + "sam9x60 8MiB SDRAM SiP", "sam9x60"), + #endif + #ifdef CONFIG_SOC_SAMA5 +-- +2.35.1 + diff --git a/queue-5.15/arm-at91-pm-use-proper-compatible-for-sama5d2-s-rtc.patch b/queue-5.15/arm-at91-pm-use-proper-compatible-for-sama5d2-s-rtc.patch new file mode 100644 index 00000000000..2e7472bb66d --- /dev/null +++ b/queue-5.15/arm-at91-pm-use-proper-compatible-for-sama5d2-s-rtc.patch @@ -0,0 +1,36 @@ +From a855b8d8317db78495bf3094866ae0a54ac1d445 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 23 May 2022 12:24:19 +0300 +Subject: ARM: at91: pm: use proper compatible for sama5d2's rtc + +From: Claudiu Beznea + +[ Upstream commit ddc980da8043779119acaca106c6d9b445c9b65b ] + +Use proper compatible strings for SAMA5D2's RTC IPs. This is necessary +for configuring wakeup sources for ULP1 PM mode. + +Fixes: d7484f5c6b3b ("ARM: at91: pm: configure wakeup sources for ULP1 mode") +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20220523092421.317345-2-claudiu.beznea@microchip.com +Signed-off-by: Sasha Levin +--- + arch/arm/mach-at91/pm.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c +index 8711d6824c1f..cde99c9d0b2e 100644 +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -146,7 +146,7 @@ static const struct wakeup_source_info ws_info[] = { + + static const struct of_device_id sama5d2_ws_ids[] = { + { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] }, +- { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] }, ++ { .compatible = "atmel,sama5d2-rtc", .data = &ws_info[1] }, + { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] }, + { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, + { .compatible = "usb-ohci", .data = &ws_info[2] }, +-- +2.35.1 + diff --git a/queue-5.15/arm-at91-pm-use-proper-compatibles-for-sam9x60-s-rtc.patch b/queue-5.15/arm-at91-pm-use-proper-compatibles-for-sam9x60-s-rtc.patch new file mode 100644 index 00000000000..b3090ba601e --- /dev/null +++ b/queue-5.15/arm-at91-pm-use-proper-compatibles-for-sam9x60-s-rtc.patch @@ -0,0 +1,42 @@ +From 27ac83661fc2d13e5ee6ffeb283962c82daa8973 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 23 May 2022 12:24:20 +0300 +Subject: ARM: at91: pm: use proper compatibles for sam9x60's rtc and rtt + +From: Claudiu Beznea + +[ Upstream commit 641522665dbb25ce117c78746df1aad8b58c80e5 ] + +Use proper compatible strings for SAM9X60's RTC and RTT IPs. These are +necessary for configuring wakeup sources for ULP1 PM mode. + +Fixes: eaedc0d379da ("ARM: at91: pm: add ULP1 support for SAM9X60") +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20220523092421.317345-3-claudiu.beznea@microchip.com +Signed-off-by: Sasha Levin +--- + arch/arm/mach-at91/pm.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c +index cde99c9d0b2e..cbad3609b783 100644 +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -157,12 +157,12 @@ static const struct of_device_id sama5d2_ws_ids[] = { + }; + + static const struct of_device_id sam9x60_ws_ids[] = { +- { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] }, ++ { .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] }, + { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, + { .compatible = "usb-ohci", .data = &ws_info[2] }, + { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, + { .compatible = "usb-ehci", .data = &ws_info[2] }, +- { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] }, ++ { .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] }, + { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] }, + { /* sentinel */ } + }; +-- +2.35.1 + diff --git a/queue-5.15/arm-at91-pm-use-proper-compatibles-for-sama7g5-s-rtc.patch b/queue-5.15/arm-at91-pm-use-proper-compatibles-for-sama7g5-s-rtc.patch new file mode 100644 index 00000000000..333d7d9e83e --- /dev/null +++ b/queue-5.15/arm-at91-pm-use-proper-compatibles-for-sama7g5-s-rtc.patch @@ -0,0 +1,43 @@ +From cad3b560d4e341db4fd0a4e680443d68d616297d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 23 May 2022 12:24:21 +0300 +Subject: ARM: at91: pm: use proper compatibles for sama7g5's rtc and rtt + +From: Claudiu Beznea + +[ Upstream commit 1c40169b35ad58906814d53a517ac92db3d20d5f ] + +Use proper compatible strings for SAMA7G5's RTC and RTT IPs. These are +necessary for configuring wakeup sources for ULP1 PM mode. + +Fixes: 6501330f9f5e ("ARM: at91: pm: add pm support for SAMA7G5") +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20220523092421.317345-4-claudiu.beznea@microchip.com +Signed-off-by: Sasha Levin +--- + arch/arm/mach-at91/pm.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c +index cbad3609b783..ed1050404ef0 100644 +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -168,13 +168,13 @@ static const struct of_device_id sam9x60_ws_ids[] = { + }; + + static const struct of_device_id sama7g5_ws_ids[] = { +- { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] }, ++ { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] }, + { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] }, + { .compatible = "usb-ohci", .data = &ws_info[2] }, + { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, + { .compatible = "usb-ehci", .data = &ws_info[2] }, + { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] }, +- { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] }, ++ { .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] }, + { /* sentinel */ } + }; + +-- +2.35.1 + diff --git a/queue-5.15/arm-dts-at91-sam9x60ek-fix-eeprom-compatible-and-siz.patch b/queue-5.15/arm-dts-at91-sam9x60ek-fix-eeprom-compatible-and-siz.patch new file mode 100644 index 00000000000..770f9e71da8 --- /dev/null +++ b/queue-5.15/arm-dts-at91-sam9x60ek-fix-eeprom-compatible-and-siz.patch @@ -0,0 +1,43 @@ +From 3d19ae64eaafeb2ef099a17b981131e21a1ae3e5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 7 Jun 2022 12:04:54 +0300 +Subject: ARM: dts: at91: sam9x60ek: fix eeprom compatible and size + +From: Eugen Hristev + +[ Upstream commit f2cbbc3f926316ccf8ef9363d8a60c1110afc1c7 ] + +The board has a microchip 24aa025e48 eeprom, which is a 2 Kbits memory, +so it's compatible with at24c02 not at24c32. +Also the size property is wrong, it's not 128 bytes, but 256 bytes. +Thus removing and leaving it to the default (256). + +Fixes: 1e5f532c27371 ("ARM: dts: at91: sam9x60: add device tree for soc and board") +Signed-off-by: Eugen Hristev +Reviewed-by: Claudiu Beznea +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20220607090455.80433-1-eugen.hristev@microchip.com +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/at91-sam9x60ek.dts | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts +index b1068cca4228..fd8dc1183b3e 100644 +--- a/arch/arm/boot/dts/at91-sam9x60ek.dts ++++ b/arch/arm/boot/dts/at91-sam9x60ek.dts +@@ -233,10 +233,9 @@ + status = "okay"; + + eeprom@53 { +- compatible = "atmel,24c32"; ++ compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; +- size = <128>; + status = "okay"; + }; + }; +-- +2.35.1 + diff --git a/queue-5.15/arm-dts-at91-sama5d2_icp-fix-eeprom-compatibles.patch b/queue-5.15/arm-dts-at91-sama5d2_icp-fix-eeprom-compatibles.patch new file mode 100644 index 00000000000..ca502e51ed9 --- /dev/null +++ b/queue-5.15/arm-dts-at91-sama5d2_icp-fix-eeprom-compatibles.patch @@ -0,0 +1,54 @@ +From 4a1d1753875253f32d55c851ca37453da5384ca3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 7 Jun 2022 12:04:55 +0300 +Subject: ARM: dts: at91: sama5d2_icp: fix eeprom compatibles + +From: Eugen Hristev + +[ Upstream commit 416ce193d73a734ded6d09fe141017b38af1c567 ] + +The eeprom memories on the board are microchip 24aa025e48, which are 2 Kbits +and are compatible with at24c02 not at24c32. + +Fixes: 68a95ef72cefe ("ARM: dts: at91: sama5d2-icp: add SAMA5D2-ICP") +Signed-off-by: Eugen Hristev +Reviewed-by: Claudiu Beznea +Signed-off-by: Claudiu Beznea +Link: https://lore.kernel.org/r/20220607090455.80433-2-eugen.hristev@microchip.com +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/at91-sama5d2_icp.dts | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts +index e06b58724ca8..fd1a288f686b 100644 +--- a/arch/arm/boot/dts/at91-sama5d2_icp.dts ++++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts +@@ -323,21 +323,21 @@ + status = "okay"; + + eeprom@50 { +- compatible = "atmel,24c32"; ++ compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + status = "okay"; + }; + + eeprom@52 { +- compatible = "atmel,24c32"; ++ compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + status = "disabled"; + }; + + eeprom@53 { +- compatible = "atmel,24c32"; ++ compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + status = "disabled"; +-- +2.35.1 + diff --git a/queue-5.15/arm-dts-stm32-add-missing-usbh-clock-and-fix-clk-ord.patch b/queue-5.15/arm-dts-stm32-add-missing-usbh-clock-and-fix-clk-ord.patch new file mode 100644 index 00000000000..807d3ade9da --- /dev/null +++ b/queue-5.15/arm-dts-stm32-add-missing-usbh-clock-and-fix-clk-ord.patch @@ -0,0 +1,53 @@ +From fdbcbacd76af83c85290dc190bbec5102117021c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 21 Jun 2022 10:45:09 +0200 +Subject: ARM: dts: stm32: add missing usbh clock and fix clk order on + stm32mp15 + +From: Fabrice Gasnier + +[ Upstream commit 1d0c1aadf1fd9f3de95d1532b3651e8634546e71 ] + +The USBH composed of EHCI and OHCI controllers needs the PHY clock to be +initialized first, before enabling (gating) them. The reverse is also +required when going to suspend. +So, add USBPHY clock as 1st entry in both controllers, so the USBPHY PLL +gets enabled 1st upon controller init. Upon suspend/resume, this also makes +the clock to be disabled/re-enabled in the correct order. +This fixes some IRQ storm conditions seen when going to low-power, due to +PHY PLL being disabled before all clocks are cleanly gated. + +Fixes: 949a0c0dec85 ("ARM: dts: stm32: add USB Host (USBH) support to stm32mp157c") +Fixes: db7be2cb87ae ("ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151") +Signed-off-by: Fabrice Gasnier +Signed-off-by: Alexandre Torgue +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/stm32mp151.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi +index f693a7d24247..a9b65b3bfda5 100644 +--- a/arch/arm/boot/dts/stm32mp151.dtsi ++++ b/arch/arm/boot/dts/stm32mp151.dtsi +@@ -1452,7 +1452,7 @@ + usbh_ohci: usb@5800c000 { + compatible = "generic-ohci"; + reg = <0x5800c000 0x1000>; +- clocks = <&rcc USBH>, <&usbphyc>; ++ clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + status = "disabled"; +@@ -1461,7 +1461,7 @@ + usbh_ehci: usb@5800d000 { + compatible = "generic-ehci"; + reg = <0x5800d000 0x1000>; +- clocks = <&rcc USBH>; ++ clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + companion = <&usbh_ohci>; +-- +2.35.1 + diff --git a/queue-5.15/arm-dts-stm32-use-usbphyc-ck_usbo_48m-as-usbh-ohci-c.patch b/queue-5.15/arm-dts-stm32-use-usbphyc-ck_usbo_48m-as-usbh-ohci-c.patch new file mode 100644 index 00000000000..340a333a459 --- /dev/null +++ b/queue-5.15/arm-dts-stm32-use-usbphyc-ck_usbo_48m-as-usbh-ohci-c.patch @@ -0,0 +1,46 @@ +From cbc3dfa377b12e9fe594f9dedffee2610ec7aaca Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 6 Oct 2021 11:53:55 +0200 +Subject: ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on + stm32mp151 + +From: Amelie Delaunay + +[ Upstream commit db7be2cb87ae65e2d033a9f61f7fb94bce505177 ] + +Referring to the note under USBH reset and clocks chapter of RM0436, +"In order to access USBH_OHCI registers it is necessary to activate the USB +clocks by enabling the PLL controlled by USBPHYC" (ck_usbo_48m). + +The point is, when USBPHYC PLL is not enabled, OHCI register access +freezes the resume from STANDBY. It is the case when dual USBH is enabled, +instead of OTG + single USBH. +When OTG is probed, as ck_usbo_48m is USBO clock parent, then USBPHYC PLL +is enabled and OHCI register access is OK. + +This patch adds ck_usbo_48m (provided by USBPHYC PLL) as clock of USBH +OHCI, thus USBPHYC PLL will be enabled and OHCI register access will be OK. + +Signed-off-by: Amelie Delaunay +Signed-off-by: Alexandre Torgue +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/stm32mp151.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi +index 6992a4b0ba79..f693a7d24247 100644 +--- a/arch/arm/boot/dts/stm32mp151.dtsi ++++ b/arch/arm/boot/dts/stm32mp151.dtsi +@@ -1452,7 +1452,7 @@ + usbh_ohci: usb@5800c000 { + compatible = "generic-ohci"; + reg = <0x5800c000 0x1000>; +- clocks = <&rcc USBH>; ++ clocks = <&rcc USBH>, <&usbphyc>; + resets = <&rcc USBH_R>; + interrupts = ; + status = "disabled"; +-- +2.35.1 + diff --git a/queue-5.15/arm-meson-fix-refcount-leak-in-meson_smp_prepare_cpu.patch b/queue-5.15/arm-meson-fix-refcount-leak-in-meson_smp_prepare_cpu.patch new file mode 100644 index 00000000000..5f73a029a32 --- /dev/null +++ b/queue-5.15/arm-meson-fix-refcount-leak-in-meson_smp_prepare_cpu.patch @@ -0,0 +1,46 @@ +From 4daa88027bf367f1cca6bc9395fe96014e7582eb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 12 May 2022 06:16:10 +0400 +Subject: ARM: meson: Fix refcount leak in meson_smp_prepare_cpus + +From: Miaoqian Lin + +[ Upstream commit 34d2cd3fccced12b958b8848e3eff0ee4296764c ] + +of_find_compatible_node() returns a node pointer with refcount +incremented, we should use of_node_put() on it when done. +Add missing of_node_put() to avoid refcount leak. + +Fixes: d850f3e5d296 ("ARM: meson: Add SMP bringup code for Meson8 and Meson8b") +Signed-off-by: Miaoqian Lin +Reviewed-by: Martin Blumenstingl +Signed-off-by: Neil Armstrong +Link: https://lore.kernel.org/r/20220512021611.47921-1-linmq006@gmail.com +Signed-off-by: Sasha Levin +--- + arch/arm/mach-meson/platsmp.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/mach-meson/platsmp.c b/arch/arm/mach-meson/platsmp.c +index 4b8ad728bb42..32ac60b89fdc 100644 +--- a/arch/arm/mach-meson/platsmp.c ++++ b/arch/arm/mach-meson/platsmp.c +@@ -71,6 +71,7 @@ static void __init meson_smp_prepare_cpus(const char *scu_compatible, + } + + sram_base = of_iomap(node, 0); ++ of_node_put(node); + if (!sram_base) { + pr_err("Couldn't map SRAM registers\n"); + return; +@@ -91,6 +92,7 @@ static void __init meson_smp_prepare_cpus(const char *scu_compatible, + } + + scu_base = of_iomap(node, 0); ++ of_node_put(node); + if (!scu_base) { + pr_err("Couldn't map SCU registers\n"); + return; +-- +2.35.1 + diff --git a/queue-5.15/arm-mxs_defconfig-enable-the-framebuffer.patch b/queue-5.15/arm-mxs_defconfig-enable-the-framebuffer.patch new file mode 100644 index 00000000000..30d280885bb --- /dev/null +++ b/queue-5.15/arm-mxs_defconfig-enable-the-framebuffer.patch @@ -0,0 +1,43 @@ +From d2da9021863f469c813b42ecda0799c4774d8514 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 21 Jun 2022 13:45:05 -0300 +Subject: ARM: mxs_defconfig: Enable the framebuffer + +From: Fabio Estevam + +[ Upstream commit b10ef5f2ddb3a5a22ac0936c8d91a50ac5e55e77 ] + +Currently, when booting Linux on a imx28-evk board there is +no display activity. + +Enable CONFIG_FB which is nowadays required for CONFIG_DRM_PANEL_LVDS, +CONFIG_DRM_PANEL_SIMPLE, CONFIG_DRM_PANEL_SEIKO_43WVF1G, +CONFIG_FB_MODE_HELPERS, CONFIG_BACKLIGHT_PWM, CONFIG_BACKLIGHT_GPIO, +CONFIG_FRAMEBUFFER_CONSOLE, CONFIG_LOGO, CONFIG_FONTS, CONFIG_FONT_8x8 +and CONFIG_FONT_8x16. + +Based on commit c54467482ffd ("ARM: imx_v6_v7_defconfig: enable fb"). + +Fixes: f611b1e7624c ("drm: Avoid circular dependencies for CONFIG_FB") +Signed-off-by: Fabio Estevam +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm/configs/mxs_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig +index ca32446b187f..f53086ddc48b 100644 +--- a/arch/arm/configs/mxs_defconfig ++++ b/arch/arm/configs/mxs_defconfig +@@ -93,6 +93,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y + CONFIG_DRM=y + CONFIG_DRM_PANEL_SEIKO_43WVF1G=y + CONFIG_DRM_MXSFB=y ++CONFIG_FB=y + CONFIG_FB_MODE_HELPERS=y + CONFIG_LCD_CLASS_DEVICE=y + CONFIG_BACKLIGHT_CLASS_DEVICE=y +-- +2.35.1 + diff --git a/queue-5.15/arm64-dts-imx8mp-evk-correct-eqos-pad-settings.patch b/queue-5.15/arm64-dts-imx8mp-evk-correct-eqos-pad-settings.patch new file mode 100644 index 00000000000..9b9fbc44ee9 --- /dev/null +++ b/queue-5.15/arm64-dts-imx8mp-evk-correct-eqos-pad-settings.patch @@ -0,0 +1,68 @@ +From 597e69e53f4f4daead811c72779bf06f1ab9ff99 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Jun 2022 14:14:01 +0800 +Subject: arm64: dts: imx8mp-evk: correct eqos pad settings + +From: Peng Fan + +[ Upstream commit e6e1bc0ec9e8ad212fa46d8878a6e17cd31fdf7b ] + +According to RM bit layout, BIT3 and BIT0 are reserved. + 8 7 6 5 4 3 2 1 0 +PE HYS PUE ODE FSEL X DSE X + +Although function is not broken, we should not set reserved bit. + +Fixes: dc6d5dc89bad ("arm64: dts: imx8mp-evk: enable EQOS ethernet") +Signed-off-by: Peng Fan +Reviewed-by: Rasmus Villemoes +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 30 ++++++++++---------- + 1 file changed, 15 insertions(+), 15 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +index c794e8662da8..33664c217673 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +@@ -285,21 +285,21 @@ + &iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < +- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 +- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 +- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 +- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 +- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 +- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 +- MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 +- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 +- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f +- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f +- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f +- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f +- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f +- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f +- MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 ++ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 ++ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 ++ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 ++ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 ++ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 ++ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 ++ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 ++ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 ++ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 ++ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 ++ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 ++ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 ++ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 ++ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 ++ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 + >; + }; + +-- +2.35.1 + diff --git a/queue-5.15/arm64-dts-imx8mp-evk-correct-gpio-led-pad-settings.patch b/queue-5.15/arm64-dts-imx8mp-evk-correct-gpio-led-pad-settings.patch new file mode 100644 index 00000000000..4a938275233 --- /dev/null +++ b/queue-5.15/arm64-dts-imx8mp-evk-correct-gpio-led-pad-settings.patch @@ -0,0 +1,41 @@ +From 97f469138b0aaa76c6f39fa8058149c13079b288 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Jun 2022 14:13:59 +0800 +Subject: arm64: dts: imx8mp-evk: correct gpio-led pad settings + +From: Peng Fan + +[ Upstream commit b838582ab8d5fb11b2c0275056a9f34e1d94fece ] + +0x19 is not a valid setting. According to RM bit layout, +BIT3 and BIT0 are reserved. + 8 7 6 5 4 3 2 1 0 + PE HYS PUE ODE FSEL X DSE X + +Correct setting with PE PUE set, DSE set to 0. + +Fixes: 50d336b12f34 ("arm64: dts: imx8mp-evk: Add GPIO LED support") +Signed-off-by: Peng Fan +Reviewed-by: Rasmus Villemoes +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +index 3f424a8937f1..be3b01b5e159 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +@@ -351,7 +351,7 @@ + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < +- MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 ++ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 + >; + }; + +-- +2.35.1 + diff --git a/queue-5.15/arm64-dts-imx8mp-evk-correct-i2c1-pad-settings.patch b/queue-5.15/arm64-dts-imx8mp-evk-correct-i2c1-pad-settings.patch new file mode 100644 index 00000000000..8840d38017e --- /dev/null +++ b/queue-5.15/arm64-dts-imx8mp-evk-correct-i2c1-pad-settings.patch @@ -0,0 +1,42 @@ +From afb4339a365e147eb2e3a4c41af903482312738b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Jun 2022 14:14:04 +0800 +Subject: arm64: dts: imx8mp-evk: correct I2C1 pad settings + +From: Peng Fan + +[ Upstream commit 05a7f43478e890513d571f36660bfedc1482a588 ] + +According to RM bit layout, BIT3 and BIT0 are reserved. + 8 7 6 5 4 3 2 1 0 +PE HYS PUE ODE FSEL X DSE X + +Although function is not broken, we should not set reserved bit. + +Fixes: 5497bc2a2bff ("arm64: dts: imx8mp-evk: Add PMIC device") +Signed-off-by: Peng Fan +Reviewed-by: Rasmus Villemoes +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +index 33664c217673..de6f3297fea4 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +@@ -357,8 +357,8 @@ + + pinctrl_i2c1: i2c1grp { + fsl,pins = < +- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 +- MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 ++ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 ++ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + +-- +2.35.1 + diff --git a/queue-5.15/arm64-dts-imx8mp-evk-correct-i2c3-pad-settings.patch b/queue-5.15/arm64-dts-imx8mp-evk-correct-i2c3-pad-settings.patch new file mode 100644 index 00000000000..95b2fef2bc9 --- /dev/null +++ b/queue-5.15/arm64-dts-imx8mp-evk-correct-i2c3-pad-settings.patch @@ -0,0 +1,42 @@ +From c0e189ab6f5b760108b66dd0d4c9aae745b1ba3c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Jun 2022 14:14:05 +0800 +Subject: arm64: dts: imx8mp-evk: correct I2C3 pad settings + +From: Peng Fan + +[ Upstream commit 0836de513ebaae5f03014641eac996290d67493d ] + +According to RM bit layout, BIT3 and BIT0 are reserved. + 8 7 6 5 4 3 2 1 0 +PE HYS PUE ODE FSEL X DSE X + +Although function is not broken, we should not set reserved bit. + +Fixes: 5e4a67ff7f69 ("arm64: dts: imx8mp-evk: Add i2c3 support") +Signed-off-by: Peng Fan +Reviewed-by: Rasmus Villemoes +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +index de6f3297fea4..5c9fb39dd99e 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +@@ -364,8 +364,8 @@ + + pinctrl_i2c3: i2c3grp { + fsl,pins = < +- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 +- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 ++ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 ++ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + +-- +2.35.1 + diff --git a/queue-5.15/arm64-dts-imx8mp-evk-correct-mmc-pad-settings.patch b/queue-5.15/arm64-dts-imx8mp-evk-correct-mmc-pad-settings.patch new file mode 100644 index 00000000000..7cb7a2492f7 --- /dev/null +++ b/queue-5.15/arm64-dts-imx8mp-evk-correct-mmc-pad-settings.patch @@ -0,0 +1,67 @@ +From b3789b5c79ed2f93cc95dd0256790221b6c91d7b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Jun 2022 14:13:57 +0800 +Subject: arm64: dts: imx8mp-evk: correct mmc pad settings + +From: Peng Fan + +[ Upstream commit 01785f1f156511c4f285786b4192245d4f476bf1 ] + +According to RM bit layout, BIT3 and BIT0 are reserved. + 8 7 6 5 4 3 2 1 0 + PE HYS PUE ODE FSEL X DSE X + +Not set reserved bit. + +Fixes: 9e847693c6f3 ("arm64: dts: freescale: Add i.MX8MP EVK board support") +Signed-off-by: Peng Fan +Reviewed-by: Rasmus Villemoes +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +index 7b99fad6e4d6..3c4369d6468c 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +@@ -377,7 +377,7 @@ + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < +- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 ++ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + +@@ -402,7 +402,7 @@ + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 +- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 ++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + +@@ -414,7 +414,7 @@ + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 +- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 ++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + +@@ -426,7 +426,7 @@ + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 +- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 ++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + +-- +2.35.1 + diff --git a/queue-5.15/arm64-dts-imx8mp-evk-correct-the-uart2-pinctl-value.patch b/queue-5.15/arm64-dts-imx8mp-evk-correct-the-uart2-pinctl-value.patch new file mode 100644 index 00000000000..5f7786e545e --- /dev/null +++ b/queue-5.15/arm64-dts-imx8mp-evk-correct-the-uart2-pinctl-value.patch @@ -0,0 +1,44 @@ +From e2682f85930afa8f5322bc6f6dd6ff991fe6b813 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Jun 2022 14:13:58 +0800 +Subject: arm64: dts: imx8mp-evk: correct the uart2 pinctl value + +From: Sherry Sun + +[ Upstream commit 2d4fb72b681205eed4553d8802632bd3270be3ba ] + +According to the IOMUXC_SW_PAD_CTL_PAD_UART2_RXD/TXD register define in +imx8mp RM, bit0 and bit3 are reserved, and the uart2 rx/tx pin should +enable the pull up, so need to set bit8 to 1. The original pinctl value +0x49 is incorrect and needs to be changed to 0x140, same as uart1 and +uart3. + +Fixes: 9e847693c6f3 ("arm64: dts: freescale: Add i.MX8MP EVK board support") +Reviewed-by: Haibo Chen +Signed-off-by: Sherry Sun +Signed-off-by: Peng Fan +Reviewed-by: Rasmus Villemoes +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +index 3c4369d6468c..3f424a8937f1 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +@@ -383,8 +383,8 @@ + + pinctrl_uart2: uart2grp { + fsl,pins = < +- MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 +- MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 ++ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 ++ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + +-- +2.35.1 + diff --git a/queue-5.15/arm64-dts-imx8mp-evk-correct-vbus-pad-settings.patch b/queue-5.15/arm64-dts-imx8mp-evk-correct-vbus-pad-settings.patch new file mode 100644 index 00000000000..25cc7f81e8c --- /dev/null +++ b/queue-5.15/arm64-dts-imx8mp-evk-correct-vbus-pad-settings.patch @@ -0,0 +1,41 @@ +From 328d44fa01b197aa30d5a7e1d84413c5d26e154f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Jun 2022 14:14:00 +0800 +Subject: arm64: dts: imx8mp-evk: correct vbus pad settings + +From: Peng Fan + +[ Upstream commit e2c00820a99c55c9bb40642d5818a904a1e0d664 ] + +0x19 is not a valid setting. According to RM bit layout, BIT3 and BIT0 +are reserved. + 8 7 6 5 4 3 2 1 0 + PE HYS PUE ODE FSEL X DSE X + +Not set reserved bit. + +Fixes: 43da4f92a611 ("arm64: dts: imx8mp-evk: enable usb1 as host mode") +Signed-off-by: Peng Fan +Reviewed-by: Rasmus Villemoes +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +index be3b01b5e159..c794e8662da8 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +@@ -390,7 +390,7 @@ + + pinctrl_usb1_vbus: usb1grp { + fsl,pins = < +- MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19 ++ MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 + >; + }; + +-- +2.35.1 + diff --git a/queue-5.15/arm64-dts-imx8mp-phyboard-pollux-rdk-correct-eqos-pa.patch b/queue-5.15/arm64-dts-imx8mp-phyboard-pollux-rdk-correct-eqos-pa.patch new file mode 100644 index 00000000000..49ec51a6b3d --- /dev/null +++ b/queue-5.15/arm64-dts-imx8mp-phyboard-pollux-rdk-correct-eqos-pa.patch @@ -0,0 +1,62 @@ +From 2f661e11dff53718856d4c2becb650494d705b3f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Jun 2022 14:14:08 +0800 +Subject: arm64: dts: imx8mp-phyboard-pollux-rdk: correct eqos pad settings + +From: Peng Fan + +[ Upstream commit bae4de618efe1c41d34aa2e6cef8b08e46256667 ] + +BIT3 and BIT0 are reserved bits, should not touch. + +Fixes: 6f96852619d5 ("arm64: dts: freescale: Add support EQOS MAC on phyBOARD-Pollux-i.MX8MP") +Signed-off-by: Peng Fan +Reviewed-by: Rasmus Villemoes +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + .../freescale/imx8mp-phyboard-pollux-rdk.dts | 28 +++++++++---------- + 1 file changed, 14 insertions(+), 14 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +index e34076954897..cefd3d36f93f 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +@@ -116,20 +116,20 @@ + &iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < +- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 +- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 +- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 +- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 +- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 +- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 +- MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 +- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 +- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f +- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f +- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f +- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f +- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f +- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f ++ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 ++ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 ++ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 ++ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 ++ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 ++ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 ++ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 ++ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 ++ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 ++ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 ++ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 ++ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 ++ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 ++ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10 + >; + }; +-- +2.35.1 + diff --git a/queue-5.15/arm64-dts-imx8mp-phyboard-pollux-rdk-correct-i2c2-mm.patch b/queue-5.15/arm64-dts-imx8mp-phyboard-pollux-rdk-correct-i2c2-mm.patch new file mode 100644 index 00000000000..d28c41829f5 --- /dev/null +++ b/queue-5.15/arm64-dts-imx8mp-phyboard-pollux-rdk-correct-i2c2-mm.patch @@ -0,0 +1,81 @@ +From cda0a864d05191a82387e623a253cc07f926d7ab Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Jun 2022 14:14:09 +0800 +Subject: arm64: dts: imx8mp-phyboard-pollux-rdk: correct i2c2 & mmc settings + +From: Peng Fan + +[ Upstream commit 242d8ee9111171a6e68249aaff62643c513be6ec ] + +BIT3 and BIT0 are reserved bits, should not touch. + +Fixes: 88f7f6bcca37 ("arm64: dts: freescale: Add support for phyBOARD-Pollux-i.MX8MP") +Signed-off-by: Peng Fan +Reviewed-by: Rasmus Villemoes +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +index cefd3d36f93f..6aa720bafe28 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +@@ -136,21 +136,21 @@ + + pinctrl_i2c2: i2c2grp { + fsl,pins = < +- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 +- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 ++ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 ++ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < +- MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3 +- MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3 ++ MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2 ++ MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < +- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 ++ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + +@@ -175,7 +175,7 @@ + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 +- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 ++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + +@@ -187,7 +187,7 @@ + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 +- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 ++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + +@@ -199,7 +199,7 @@ + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 +- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 ++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + }; +-- +2.35.1 + diff --git a/queue-5.15/arm64-dts-imx8mp-phyboard-pollux-rdk-correct-uart-pa.patch b/queue-5.15/arm64-dts-imx8mp-phyboard-pollux-rdk-correct-uart-pa.patch new file mode 100644 index 00000000000..c83262f89b2 --- /dev/null +++ b/queue-5.15/arm64-dts-imx8mp-phyboard-pollux-rdk-correct-uart-pa.patch @@ -0,0 +1,38 @@ +From 8c3f4137a91b62cc10f7560cb6f42d82ac1edee4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Jun 2022 14:14:07 +0800 +Subject: arm64: dts: imx8mp-phyboard-pollux-rdk: correct uart pad settings + +From: Peng Fan + +[ Upstream commit e266c155bd88e95f9b86379d6b0add6ac6e5452e ] + +BIT3 and BIT0 are reserved bits, should not touch. + +Fixes: 846f752866bd ("arm64: dts: imx8mp-phyboard-pollux-rdk: Change debug UART") +Signed-off-by: Peng Fan +Reviewed-by: Rasmus Villemoes +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +index 984a6b9ded8d..e34076954897 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +@@ -156,8 +156,8 @@ + + pinctrl_uart1: uart1grp { + fsl,pins = < +- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49 +- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49 ++ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40 ++ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40 + >; + }; + +-- +2.35.1 + diff --git a/queue-5.15/arm64-dts-qcom-msm8992-fix-vdd_lvs1_2-supply-typo.patch b/queue-5.15/arm64-dts-qcom-msm8992-fix-vdd_lvs1_2-supply-typo.patch new file mode 100644 index 00000000000..d0a43e38eef --- /dev/null +++ b/queue-5.15/arm64-dts-qcom-msm8992-fix-vdd_lvs1_2-supply-typo.patch @@ -0,0 +1,67 @@ +From cf4a3cd4796e6aa7d6a9b82f0a35536d757348da Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 27 Jun 2022 15:59:38 +0200 +Subject: arm64: dts: qcom: msm8992-*: Fix vdd_lvs1_2-supply typo + +From: Stephan Gerhold + +[ Upstream commit 5fb779558f1c97e2bf2794cb59553e569c38e2f9 ] + +"make dtbs_check" complains about the missing "-supply" suffix for +vdd_lvs1_2 which is clearly a typo, originally introduced in the +msm8994-smd-rpm.dtsi file and apparently later copied to +msm8992-xiaomi-libra.dts: + +msm8992-lg-bullhead-rev-10/101.dtb: pm8994-regulators: 'vdd_lvs1_2' +does not match any of the regexes: + '.*-supply$', '^((s|l|lvs|5vs)[0-9]*)|(boost-bypass)|(bob)$', 'pinctrl-[0-9]+' +From schema: regulator/qcom,smd-rpm-regulator.yaml + +msm8992-xiaomi-libra.dtb: pm8994-regulators: 'vdd_lvs1_2' +does not match any of the regexes: + '.*-supply$', '^((s|l|lvs|5vs)[0-9]*)|(boost-bypass)|(bob)$', 'pinctrl-[0-9]+' +From schema: regulator/qcom,smd-rpm-regulator.yaml + +Reported-by: Rob Herring +Cc: Konrad Dybcio +Fixes: f3b2c99e73be ("arm64: dts: Enable onboard SDHCI on msm8992") +Fixes: 0f5cdb31e850 ("arm64: dts: qcom: Add Xiaomi Libra (Mi 4C) device tree") +Signed-off-by: Stephan Gerhold +Reviewed-by: Konrad Dybcio +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220627135938.2901871-1-stephan.gerhold@kernkonzept.com +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts | 2 +- + arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts +index 1ccca83292ac..c7d191dc6d4b 100644 +--- a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts ++++ b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts +@@ -74,7 +74,7 @@ + vdd_l17_29-supply = <&vph_pwr>; + vdd_l20_21-supply = <&vph_pwr>; + vdd_l25-supply = <&pm8994_s5>; +- vdd_lvs1_2 = <&pm8994_s4>; ++ vdd_lvs1_2-supply = <&pm8994_s4>; + + /* S1, S2, S6 and S12 are managed by RPMPD */ + +diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +index 357d55496e75..a3d6340a0c55 100644 +--- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts ++++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +@@ -142,7 +142,7 @@ + vdd_l17_29-supply = <&vph_pwr>; + vdd_l20_21-supply = <&vph_pwr>; + vdd_l25-supply = <&pm8994_s5>; +- vdd_lvs1_2 = <&pm8994_s4>; ++ vdd_lvs1_2-supply = <&pm8994_s4>; + + /* S1, S2, S6 and S12 are managed by RPMPD */ + +-- +2.35.1 + diff --git a/queue-5.15/arm64-dts-qcom-msm8994-fix-cpu6-7-reg-values.patch b/queue-5.15/arm64-dts-qcom-msm8994-fix-cpu6-7-reg-values.patch new file mode 100644 index 00000000000..e01768585dd --- /dev/null +++ b/queue-5.15/arm64-dts-qcom-msm8994-fix-cpu6-7-reg-values.patch @@ -0,0 +1,45 @@ +From d96b8ab3df364a2ebd3abe74e542fcd2087e0d58 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 1 May 2022 20:40:16 +0200 +Subject: arm64: dts: qcom: msm8994: Fix CPU6/7 reg values + +From: Konrad Dybcio + +[ Upstream commit 47bf59c4755930f616dd90c8c6a85f40a6d347ea ] + +CPU6 and CPU7 were mistakengly pointing to CPU5 reg. Fix it. + +Fixes: 02d8091bbca0 ("arm64: dts: qcom: msm8994: Add a proper CPU map") +Signed-off-by: Konrad Dybcio +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220501184016.64138-1-konrad.dybcio@somainline.org +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi +index 3c27671c8b5c..a8dc8163ee82 100644 +--- a/arch/arm64/boot/dts/qcom/msm8994.dtsi ++++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi +@@ -93,7 +93,7 @@ + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; +- reg = <0x0 0x101>; ++ reg = <0x0 0x102>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; +@@ -101,7 +101,7 @@ + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; +- reg = <0x0 0x101>; ++ reg = <0x0 0x103>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; +-- +2.35.1 + diff --git a/queue-5.15/arm64-dts-qcom-sdm845-use-dispcc-ahb-clock-for-mdss-.patch b/queue-5.15/arm64-dts-qcom-sdm845-use-dispcc-ahb-clock-for-mdss-.patch new file mode 100644 index 00000000000..14279a2eab9 --- /dev/null +++ b/queue-5.15/arm64-dts-qcom-sdm845-use-dispcc-ahb-clock-for-mdss-.patch @@ -0,0 +1,39 @@ +From a03f908e9c06f726d471c976317a749a1bc06e06 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 31 May 2022 15:47:35 +0300 +Subject: arm64: dts: qcom: sdm845: use dispcc AHB clock for mdss node + +From: Dmitry Baryshkov + +[ Upstream commit 3ba500dee327e0261e728edec8a4f2f563d2760c ] + +It was noticed that on sdm845 after an MDSS suspend/resume cycle the +driver can not read HW_REV registers properly (they will return 0 +instead). Chaning the "iface" clock from <&gcc GCC_DISP_AHB_CLK> to +<&dispcc DISP_CC_MDSS_AHB_CLK> fixes the issue. + +Fixes: 08c2a076d18f ("arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file") +Signed-off-by: Dmitry Baryshkov +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20220531124735.1165582-1-dmitry.baryshkov@linaro.org +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi +index d20eacfc1017..ea7a272d267a 100644 +--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi ++++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi +@@ -4147,7 +4147,7 @@ + + power-domains = <&dispcc MDSS_GDSC>; + +- clocks = <&gcc GCC_DISP_AHB_CLK>, ++ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "core"; + +-- +2.35.1 + diff --git a/queue-5.15/asoc-codecs-rt700-rt711-rt711-sdca-resume-bus-codec-.patch b/queue-5.15/asoc-codecs-rt700-rt711-rt711-sdca-resume-bus-codec-.patch new file mode 100644 index 00000000000..e75d01c7e33 --- /dev/null +++ b/queue-5.15/asoc-codecs-rt700-rt711-rt711-sdca-resume-bus-codec-.patch @@ -0,0 +1,202 @@ +From 93b3313e13930290bccd78abd610cdec7f19f659 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 6 Jun 2022 15:37:52 -0500 +Subject: ASoC: codecs: rt700/rt711/rt711-sdca: resume bus/codec in + .set_jack_detect + +From: Pierre-Louis Bossart + +[ Upstream commit 40737057b48f1b4db67b0d766b95c87ba8fc5e03 ] + +The .set_jack_detect() codec component callback is invoked during card +registration, which happens when the machine driver is probed. + +The issue is that this callback can race with the bus suspend/resume, +and IO timeouts can happen. This can be reproduced very easily if the +machine driver is 'blacklisted' and manually probed after the bus +suspends. The bus and codec need to be re-initialized using pm_runtime +helpers. + +Previous contributions tried to make sure accesses to the bus during +the .set_jack_detect() component callback only happen when the bus is +active. This was done by changing the regcache status on a component +remove. This is however a layering violation, the regcache status +should only be modified on device probe, suspend and resume. The +component probe/remove should not modify how the device regcache is +handled. This solution also didn't handle all the possible race +conditions, and the RT700 headset codec was not handled. + +This patch tries to resume the codec device before handling the jack +initializations. In case the codec has not yet been initialized, +pm_runtime may not be enabled yet, so we don't squelch the -EACCES +error code and only stop the jack information. When the codec reports +as attached, the jack initialization will proceed as usual. + +BugLink: https://github.com/thesofproject/linux/issues/3643 +Fixes: 7ad4d237e7c4a ('ASoC: rt711-sdca: Add RT711 SDCA vendor-specific driver') +Fixes: 899b12542b089 ('ASoC: rt711: add snd_soc_component remove callback') +Signed-off-by: Pierre-Louis Bossart +Reviewed-by: Rander Wang +Reviewed-by: Bard Liao +Link: https://lore.kernel.org/r/20220606203752.144159-8-pierre-louis.bossart@linux.intel.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/rt700.c | 16 +++++++++++++--- + sound/soc/codecs/rt711-sdca.c | 26 ++++++++++++++------------ + sound/soc/codecs/rt711.c | 24 +++++++++++++----------- + 3 files changed, 40 insertions(+), 26 deletions(-) + +diff --git a/sound/soc/codecs/rt700.c b/sound/soc/codecs/rt700.c +index 921382724f9c..614a40247679 100644 +--- a/sound/soc/codecs/rt700.c ++++ b/sound/soc/codecs/rt700.c +@@ -315,17 +315,27 @@ static int rt700_set_jack_detect(struct snd_soc_component *component, + struct snd_soc_jack *hs_jack, void *data) + { + struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component); ++ int ret; + + rt700->hs_jack = hs_jack; + +- if (!rt700->hw_init) { +- dev_dbg(&rt700->slave->dev, +- "%s hw_init not ready yet\n", __func__); ++ ret = pm_runtime_resume_and_get(component->dev); ++ if (ret < 0) { ++ if (ret != -EACCES) { ++ dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret); ++ return ret; ++ } ++ ++ /* pm_runtime not enabled yet */ ++ dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__); + return 0; + } + + rt700_jack_init(rt700); + ++ pm_runtime_mark_last_busy(component->dev); ++ pm_runtime_put_autosuspend(component->dev); ++ + return 0; + } + +diff --git a/sound/soc/codecs/rt711-sdca.c b/sound/soc/codecs/rt711-sdca.c +index b168e9303ea9..c15fb98eac86 100644 +--- a/sound/soc/codecs/rt711-sdca.c ++++ b/sound/soc/codecs/rt711-sdca.c +@@ -487,16 +487,27 @@ static int rt711_sdca_set_jack_detect(struct snd_soc_component *component, + struct snd_soc_jack *hs_jack, void *data) + { + struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component); ++ int ret; + + rt711->hs_jack = hs_jack; + +- if (!rt711->hw_init) { +- dev_dbg(&rt711->slave->dev, +- "%s hw_init not ready yet\n", __func__); ++ ret = pm_runtime_resume_and_get(component->dev); ++ if (ret < 0) { ++ if (ret != -EACCES) { ++ dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret); ++ return ret; ++ } ++ ++ /* pm_runtime not enabled yet */ ++ dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__); + return 0; + } + + rt711_sdca_jack_init(rt711); ++ ++ pm_runtime_mark_last_busy(component->dev); ++ pm_runtime_put_autosuspend(component->dev); ++ + return 0; + } + +@@ -1190,14 +1201,6 @@ static int rt711_sdca_probe(struct snd_soc_component *component) + return 0; + } + +-static void rt711_sdca_remove(struct snd_soc_component *component) +-{ +- struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component); +- +- regcache_cache_only(rt711->regmap, true); +- regcache_cache_only(rt711->mbq_regmap, true); +-} +- + static const struct snd_soc_component_driver soc_sdca_dev_rt711 = { + .probe = rt711_sdca_probe, + .controls = rt711_sdca_snd_controls, +@@ -1207,7 +1210,6 @@ static const struct snd_soc_component_driver soc_sdca_dev_rt711 = { + .dapm_routes = rt711_sdca_audio_map, + .num_dapm_routes = ARRAY_SIZE(rt711_sdca_audio_map), + .set_jack = rt711_sdca_set_jack_detect, +- .remove = rt711_sdca_remove, + .endianness = 1, + }; + +diff --git a/sound/soc/codecs/rt711.c b/sound/soc/codecs/rt711.c +index 9cc7283a19c2..fafb0ba8349f 100644 +--- a/sound/soc/codecs/rt711.c ++++ b/sound/soc/codecs/rt711.c +@@ -450,17 +450,27 @@ static int rt711_set_jack_detect(struct snd_soc_component *component, + struct snd_soc_jack *hs_jack, void *data) + { + struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component); ++ int ret; + + rt711->hs_jack = hs_jack; + +- if (!rt711->hw_init) { +- dev_dbg(&rt711->slave->dev, +- "%s hw_init not ready yet\n", __func__); ++ ret = pm_runtime_resume_and_get(component->dev); ++ if (ret < 0) { ++ if (ret != -EACCES) { ++ dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret); ++ return ret; ++ } ++ ++ /* pm_runtime not enabled yet */ ++ dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__); + return 0; + } + + rt711_jack_init(rt711); + ++ pm_runtime_mark_last_busy(component->dev); ++ pm_runtime_put_autosuspend(component->dev); ++ + return 0; + } + +@@ -925,13 +935,6 @@ static int rt711_probe(struct snd_soc_component *component) + return 0; + } + +-static void rt711_remove(struct snd_soc_component *component) +-{ +- struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component); +- +- regcache_cache_only(rt711->regmap, true); +-} +- + static const struct snd_soc_component_driver soc_codec_dev_rt711 = { + .probe = rt711_probe, + .set_bias_level = rt711_set_bias_level, +@@ -942,7 +945,6 @@ static const struct snd_soc_component_driver soc_codec_dev_rt711 = { + .dapm_routes = rt711_audio_map, + .num_dapm_routes = ARRAY_SIZE(rt711_audio_map), + .set_jack = rt711_set_jack_detect, +- .remove = rt711_remove, + .endianness = 1, + }; + +-- +2.35.1 + diff --git a/queue-5.15/asoc-rt711-add-endianness-flag-in-snd_soc_component_.patch b/queue-5.15/asoc-rt711-add-endianness-flag-in-snd_soc_component_.patch new file mode 100644 index 00000000000..76afd64108e --- /dev/null +++ b/queue-5.15/asoc-rt711-add-endianness-flag-in-snd_soc_component_.patch @@ -0,0 +1,37 @@ +From b7c3061a4ba5c2e878b04518446646b0dc00daaa Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 4 May 2022 18:08:57 +0100 +Subject: ASoC: rt711: Add endianness flag in snd_soc_component_driver + +From: Charles Keepax + +[ Upstream commit 33f06beac3ade10834a82ad4105dcd91d4b00d61 ] + +The endianness flag is used on the CODEC side to specify an +ambivalence to endian, typically because it is lost over the hardware +link. This device receives audio over a SoundWire DAI and as such +should have endianness applied. + +Signed-off-by: Charles Keepax +Link: https://lore.kernel.org/r/20220504170905.332415-31-ckeepax@opensource.cirrus.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/rt711.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/sound/soc/codecs/rt711.c b/sound/soc/codecs/rt711.c +index a7c5608a0ef8..9cc7283a19c2 100644 +--- a/sound/soc/codecs/rt711.c ++++ b/sound/soc/codecs/rt711.c +@@ -943,6 +943,7 @@ static const struct snd_soc_component_driver soc_codec_dev_rt711 = { + .num_dapm_routes = ARRAY_SIZE(rt711_audio_map), + .set_jack = rt711_set_jack_detect, + .remove = rt711_remove, ++ .endianness = 1, + }; + + static int rt711_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, +-- +2.35.1 + diff --git a/queue-5.15/asoc-rt711-sdca-add-endianness-flag-in-snd_soc_compo.patch b/queue-5.15/asoc-rt711-sdca-add-endianness-flag-in-snd_soc_compo.patch new file mode 100644 index 00000000000..eff1c6f2ba5 --- /dev/null +++ b/queue-5.15/asoc-rt711-sdca-add-endianness-flag-in-snd_soc_compo.patch @@ -0,0 +1,37 @@ +From b94d2c40c7389f9844e16e5e3203f4b9e57afa1a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 4 May 2022 18:08:58 +0100 +Subject: ASoC: rt711-sdca: Add endianness flag in snd_soc_component_driver + +From: Charles Keepax + +[ Upstream commit 3e50a5001055d79c04ea1c79fe4b4ff937a3339c ] + +The endianness flag is used on the CODEC side to specify an +ambivalence to endian, typically because it is lost over the hardware +link. This device receives audio over a SoundWire DAI and as such +should have endianness applied. + +Signed-off-by: Charles Keepax +Link: https://lore.kernel.org/r/20220504170905.332415-32-ckeepax@opensource.cirrus.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + sound/soc/codecs/rt711-sdca.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/sound/soc/codecs/rt711-sdca.c b/sound/soc/codecs/rt711-sdca.c +index 2e992589f1e4..b168e9303ea9 100644 +--- a/sound/soc/codecs/rt711-sdca.c ++++ b/sound/soc/codecs/rt711-sdca.c +@@ -1208,6 +1208,7 @@ static const struct snd_soc_component_driver soc_sdca_dev_rt711 = { + .num_dapm_routes = ARRAY_SIZE(rt711_sdca_audio_map), + .set_jack = rt711_sdca_set_jack_detect, + .remove = rt711_sdca_remove, ++ .endianness = 1, + }; + + static int rt711_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, +-- +2.35.1 + diff --git a/queue-5.15/i2c-cadence-unregister-the-clk-notifier-in-error-pat.patch b/queue-5.15/i2c-cadence-unregister-the-clk-notifier-in-error-pat.patch new file mode 100644 index 00000000000..71d3684cb2b --- /dev/null +++ b/queue-5.15/i2c-cadence-unregister-the-clk-notifier-in-error-pat.patch @@ -0,0 +1,37 @@ +From 199ebce494808e50d49ca4750b6b86dcea9cb25b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Jun 2022 12:12:16 -0700 +Subject: i2c: cadence: Unregister the clk notifier in error path + +From: Satish Nagireddy + +[ Upstream commit 3501f0c663063513ad604fb1b3f06af637d3396d ] + +This patch ensures that the clock notifier is unregistered +when driver probe is returning error. + +Fixes: df8eb5691c48 ("i2c: Add driver for Cadence I2C controller") +Signed-off-by: Satish Nagireddy +Tested-by: Lars-Peter Clausen +Reviewed-by: Michal Simek +Signed-off-by: Wolfram Sang +Signed-off-by: Sasha Levin +--- + drivers/i2c/busses/i2c-cadence.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c +index b4c1ad19cdae..3d6f8ee355bf 100644 +--- a/drivers/i2c/busses/i2c-cadence.c ++++ b/drivers/i2c/busses/i2c-cadence.c +@@ -1338,6 +1338,7 @@ static int cdns_i2c_probe(struct platform_device *pdev) + return 0; + + err_clk_dis: ++ clk_notifier_unregister(id->clk, &id->clk_rate_change_nb); + clk_disable_unprepare(id->clk); + pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); +-- +2.35.1 + diff --git a/queue-5.15/i2c-piix4-fix-a-memory-leak-in-the-efch-mmio-support.patch b/queue-5.15/i2c-piix4-fix-a-memory-leak-in-the-efch-mmio-support.patch new file mode 100644 index 00000000000..f4f9eca712d --- /dev/null +++ b/queue-5.15/i2c-piix4-fix-a-memory-leak-in-the-efch-mmio-support.patch @@ -0,0 +1,85 @@ +From 052732edfd2dd4b5abe089f12018c3553a199551 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 22 Jun 2022 08:37:43 +0200 +Subject: i2c: piix4: Fix a memory leak in the EFCH MMIO support + +From: Jean Delvare + +[ Upstream commit 8ad59b397f86a4d8014966fdc0552095a0c4fb2b ] + +The recently added support for EFCH MMIO regions introduced a memory +leak in that code path. The leak is caused by the fact that +release_resource() merely removes the resource from the tree but does +not free its memory. We need to call release_mem_region() instead, +which does free the memory. As a nice side effect, this brings back +some symmetry between the legacy and MMIO paths. + +Signed-off-by: Jean Delvare +Reported-by: Yi Zhang +Tested-by: Yi Zhang +Reviewed-by: Terry Bowman +Tested-by: Terry Bowman +Fixes: 7c148722d074 ("i2c: piix4: Add EFCH MMIO support to region request and release") +Signed-off-by: Wolfram Sang +Signed-off-by: Sasha Levin +--- + drivers/i2c/busses/i2c-piix4.c | 16 +++++++--------- + 1 file changed, 7 insertions(+), 9 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c +index ac8e7d60672a..39cb1b7bb865 100644 +--- a/drivers/i2c/busses/i2c-piix4.c ++++ b/drivers/i2c/busses/i2c-piix4.c +@@ -161,7 +161,6 @@ static const char *piix4_aux_port_name_sb800 = " port 1"; + + struct sb800_mmio_cfg { + void __iomem *addr; +- struct resource *res; + bool use_mmio; + }; + +@@ -179,13 +178,11 @@ static int piix4_sb800_region_request(struct device *dev, + struct sb800_mmio_cfg *mmio_cfg) + { + if (mmio_cfg->use_mmio) { +- struct resource *res; + void __iomem *addr; + +- res = request_mem_region_muxed(SB800_PIIX4_FCH_PM_ADDR, +- SB800_PIIX4_FCH_PM_SIZE, +- "sb800_piix4_smb"); +- if (!res) { ++ if (!request_mem_region_muxed(SB800_PIIX4_FCH_PM_ADDR, ++ SB800_PIIX4_FCH_PM_SIZE, ++ "sb800_piix4_smb")) { + dev_err(dev, + "SMBus base address memory region 0x%x already in use.\n", + SB800_PIIX4_FCH_PM_ADDR); +@@ -195,12 +192,12 @@ static int piix4_sb800_region_request(struct device *dev, + addr = ioremap(SB800_PIIX4_FCH_PM_ADDR, + SB800_PIIX4_FCH_PM_SIZE); + if (!addr) { +- release_resource(res); ++ release_mem_region(SB800_PIIX4_FCH_PM_ADDR, ++ SB800_PIIX4_FCH_PM_SIZE); + dev_err(dev, "SMBus base address mapping failed.\n"); + return -ENOMEM; + } + +- mmio_cfg->res = res; + mmio_cfg->addr = addr; + + return 0; +@@ -222,7 +219,8 @@ static void piix4_sb800_region_release(struct device *dev, + { + if (mmio_cfg->use_mmio) { + iounmap(mmio_cfg->addr); +- release_resource(mmio_cfg->res); ++ release_mem_region(SB800_PIIX4_FCH_PM_ADDR, ++ SB800_PIIX4_FCH_PM_SIZE); + return; + } + +-- +2.35.1 + diff --git a/queue-5.15/i40e-fix-dropped-jumbo-frames-statistics.patch b/queue-5.15/i40e-fix-dropped-jumbo-frames-statistics.patch new file mode 100644 index 00000000000..2394d57eb2e --- /dev/null +++ b/queue-5.15/i40e-fix-dropped-jumbo-frames-statistics.patch @@ -0,0 +1,212 @@ +From 29963eb513a0aad8751e4771d47b83d31de9b73f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 31 May 2022 12:54:20 +0200 +Subject: i40e: Fix dropped jumbo frames statistics + +From: Lukasz Cieplicki + +[ Upstream commit 1adb1563e7b7ec659379a18e607e8bc3522d8a78 ] + +Dropped packets caused by too large frames were not included in +dropped RX packets statistics. +Issue was caused by not reading the GL_RXERR1 register. That register +stores count of packet which was have been dropped due to too large +size. + +Fix it by reading GL_RXERR1 register for each interface. + +Repro steps: +Send a packet larger than the set MTU to SUT +Observe rx statists: ethtool -S | grep rx | grep -v ": 0" + +Fixes: 41a9e55c89be ("i40e: add missing VSI statistics") +Signed-off-by: Lukasz Cieplicki +Signed-off-by: Jedrzej Jagielski +Tested-by: Gurucharan (A Contingent worker at Intel) +Signed-off-by: Tony Nguyen +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/intel/i40e/i40e.h | 16 ++++ + drivers/net/ethernet/intel/i40e/i40e_main.c | 73 +++++++++++++++++++ + .../net/ethernet/intel/i40e/i40e_register.h | 13 ++++ + drivers/net/ethernet/intel/i40e/i40e_type.h | 1 + + 4 files changed, 103 insertions(+) + +diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h +index 56a3a6d1dbe4..210f09118ede 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e.h ++++ b/drivers/net/ethernet/intel/i40e/i40e.h +@@ -37,6 +37,7 @@ + #include + #include + #include ++#include + #include "i40e_type.h" + #include "i40e_prototype.h" + #include +@@ -1087,6 +1088,21 @@ static inline void i40e_write_fd_input_set(struct i40e_pf *pf, + (u32)(val & 0xFFFFFFFFULL)); + } + ++/** ++ * i40e_get_pf_count - get PCI PF count. ++ * @hw: pointer to a hw. ++ * ++ * Reports the function number of the highest PCI physical ++ * function plus 1 as it is loaded from the NVM. ++ * ++ * Return: PCI PF count. ++ **/ ++static inline u32 i40e_get_pf_count(struct i40e_hw *hw) ++{ ++ return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK, ++ rd32(hw, I40E_GLGEN_PCIFCNCNT)); ++} ++ + /* needed by i40e_ethtool.c */ + int i40e_up(struct i40e_vsi *vsi); + void i40e_down(struct i40e_vsi *vsi); +diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c +index 9bc05d671ad5..02594e4d6258 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e_main.c ++++ b/drivers/net/ethernet/intel/i40e/i40e_main.c +@@ -549,6 +549,47 @@ void i40e_pf_reset_stats(struct i40e_pf *pf) + pf->hw_csum_rx_error = 0; + } + ++/** ++ * i40e_compute_pci_to_hw_id - compute index form PCI function. ++ * @vsi: ptr to the VSI to read from. ++ * @hw: ptr to the hardware info. ++ **/ ++static u32 i40e_compute_pci_to_hw_id(struct i40e_vsi *vsi, struct i40e_hw *hw) ++{ ++ int pf_count = i40e_get_pf_count(hw); ++ ++ if (vsi->type == I40E_VSI_SRIOV) ++ return (hw->port * BIT(7)) / pf_count + vsi->vf_id; ++ ++ return hw->port + BIT(7); ++} ++ ++/** ++ * i40e_stat_update64 - read and update a 64 bit stat from the chip. ++ * @hw: ptr to the hardware info. ++ * @hireg: the high 32 bit reg to read. ++ * @loreg: the low 32 bit reg to read. ++ * @offset_loaded: has the initial offset been loaded yet. ++ * @offset: ptr to current offset value. ++ * @stat: ptr to the stat. ++ * ++ * Since the device stats are not reset at PFReset, they will not ++ * be zeroed when the driver starts. We'll save the first values read ++ * and use them as offsets to be subtracted from the raw values in order ++ * to report stats that count from zero. ++ **/ ++static void i40e_stat_update64(struct i40e_hw *hw, u32 hireg, u32 loreg, ++ bool offset_loaded, u64 *offset, u64 *stat) ++{ ++ u64 new_data; ++ ++ new_data = rd64(hw, loreg); ++ ++ if (!offset_loaded || new_data < *offset) ++ *offset = new_data; ++ *stat = new_data - *offset; ++} ++ + /** + * i40e_stat_update48 - read and update a 48 bit stat from the chip + * @hw: ptr to the hardware info +@@ -620,6 +661,34 @@ static void i40e_stat_update_and_clear32(struct i40e_hw *hw, u32 reg, u64 *stat) + *stat += new_data; + } + ++/** ++ * i40e_stats_update_rx_discards - update rx_discards. ++ * @vsi: ptr to the VSI to be updated. ++ * @hw: ptr to the hardware info. ++ * @stat_idx: VSI's stat_counter_idx. ++ * @offset_loaded: ptr to the VSI's stat_offsets_loaded. ++ * @stat_offset: ptr to stat_offset to store first read of specific register. ++ * @stat: ptr to VSI's stat to be updated. ++ **/ ++static void ++i40e_stats_update_rx_discards(struct i40e_vsi *vsi, struct i40e_hw *hw, ++ int stat_idx, bool offset_loaded, ++ struct i40e_eth_stats *stat_offset, ++ struct i40e_eth_stats *stat) ++{ ++ u64 rx_rdpc, rx_rxerr; ++ ++ i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx), offset_loaded, ++ &stat_offset->rx_discards, &rx_rdpc); ++ i40e_stat_update64(hw, ++ I40E_GL_RXERR1H(i40e_compute_pci_to_hw_id(vsi, hw)), ++ I40E_GL_RXERR1L(i40e_compute_pci_to_hw_id(vsi, hw)), ++ offset_loaded, &stat_offset->rx_discards_other, ++ &rx_rxerr); ++ ++ stat->rx_discards = rx_rdpc + rx_rxerr; ++} ++ + /** + * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters. + * @vsi: the VSI to be updated +@@ -679,6 +748,10 @@ void i40e_update_eth_stats(struct i40e_vsi *vsi) + I40E_GLV_BPTCL(stat_idx), + vsi->stat_offsets_loaded, + &oes->tx_broadcast, &es->tx_broadcast); ++ ++ i40e_stats_update_rx_discards(vsi, hw, stat_idx, ++ vsi->stat_offsets_loaded, oes, es); ++ + vsi->stat_offsets_loaded = true; + } + +diff --git a/drivers/net/ethernet/intel/i40e/i40e_register.h b/drivers/net/ethernet/intel/i40e/i40e_register.h +index 1908eed4fa5e..7339003aa17c 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e_register.h ++++ b/drivers/net/ethernet/intel/i40e/i40e_register.h +@@ -211,6 +211,11 @@ + #define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0 + #define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16 + #define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT) ++#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */ ++#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0 ++#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT) ++#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16 ++#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT) + #define I40E_GLGEN_RSTAT 0x000B8188 /* Reset: POR */ + #define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0 + #define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT) +@@ -643,6 +648,14 @@ + #define I40E_VFQF_HKEY1_MAX_INDEX 12 + #define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */ + #define I40E_VFQF_HLUT1_MAX_INDEX 15 ++#define I40E_GL_RXERR1H(_i) (0x00318004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ ++#define I40E_GL_RXERR1H_MAX_INDEX 143 ++#define I40E_GL_RXERR1H_RXERR1H_SHIFT 0 ++#define I40E_GL_RXERR1H_RXERR1H_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1H_RXERR1H_SHIFT) ++#define I40E_GL_RXERR1L(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ ++#define I40E_GL_RXERR1L_MAX_INDEX 143 ++#define I40E_GL_RXERR1L_RXERR1L_SHIFT 0 ++#define I40E_GL_RXERR1L_RXERR1L_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1L_RXERR1L_SHIFT) + #define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ + #define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ + #define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ +diff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h +index 36a4ca1ffb1a..7b3f30beb757 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e_type.h ++++ b/drivers/net/ethernet/intel/i40e/i40e_type.h +@@ -1172,6 +1172,7 @@ struct i40e_eth_stats { + u64 tx_broadcast; /* bptc */ + u64 tx_discards; /* tdpc */ + u64 tx_errors; /* tepc */ ++ u64 rx_discards_other; /* rxerr1 */ + }; + + /* Statistics collected per VEB per TC */ +-- +2.35.1 + diff --git a/queue-5.15/i40e-fix-vf-s-mac-address-change-on-vm.patch b/queue-5.15/i40e-fix-vf-s-mac-address-change-on-vm.patch new file mode 100644 index 00000000000..038f089e31e --- /dev/null +++ b/queue-5.15/i40e-fix-vf-s-mac-address-change-on-vm.patch @@ -0,0 +1,49 @@ +From 1e136fec2ea60fe7f13815ab2186ee8a69f9256b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 8 Jun 2022 11:10:56 +0200 +Subject: i40e: Fix VF's MAC Address change on VM + +From: Norbert Zulinski + +[ Upstream commit fed0d9f13266a22ce1fc9a97521ef9cdc6271a23 ] + +Clear VF MAC from parent PF and remove VF filter from VSI when both +conditions are true: +-VIRTCHNL_VF_OFFLOAD_USO is not used +-VM MAC was not set from PF level + +It affects older version of IAVF and it allow them to change MAC +Address on VM, newer IAVF won't change their behaviour. + +Previously it wasn't possible to change VF's MAC Address on VM +because there is flag on IAVF driver that won't allow to +change MAC Address if this address is given from PF driver. + +Fixes: 155f0ac2c96b ("iavf: allow permanent MAC address to change") +Signed-off-by: Norbert Zulinski +Signed-off-by: Jan Sokolowski +Tested-by: Konrad Jankowski +Signed-off-by: Tony Nguyen +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c +index 6c1e668f4ebf..d78ac5e7f658 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c ++++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c +@@ -2147,6 +2147,10 @@ static int i40e_vc_get_vf_resources_msg(struct i40e_vf *vf, u8 *msg) + /* VFs only use TC 0 */ + vfres->vsi_res[0].qset_handle + = le16_to_cpu(vsi->info.qs_handle[0]); ++ if (!(vf->driver_caps & VIRTCHNL_VF_OFFLOAD_USO) && !vf->pf_set_mac) { ++ i40e_del_mac_filter(vsi, vf->default_lan_addr.addr); ++ eth_zero_addr(vf->default_lan_addr.addr); ++ } + ether_addr_copy(vfres->vsi_res[0].default_mac_addr, + vf->default_lan_addr.addr); + } +-- +2.35.1 + diff --git a/queue-5.15/ibmvnic-properly-dispose-of-all-skbs-during-a-failov.patch b/queue-5.15/ibmvnic-properly-dispose-of-all-skbs-during-a-failov.patch new file mode 100644 index 00000000000..effd53828aa --- /dev/null +++ b/queue-5.15/ibmvnic-properly-dispose-of-all-skbs-during-a-failov.patch @@ -0,0 +1,50 @@ +From 8482b4ef0c9289243e798c304bd1953455fa743f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 2 Jul 2022 03:37:12 -0700 +Subject: ibmvnic: Properly dispose of all skbs during a failover. + +From: Rick Lindsley + +[ Upstream commit 1b18f09d31cfa7148df15a7d5c5e0e86f105f7d1 ] + +During a reset, there may have been transmits in flight that are no +longer valid and cannot be fulfilled. Resetting and clearing the +queues is insufficient; each skb also needs to be explicitly freed +so that upper levels are not left waiting for confirmation of a +transmit that will never happen. If this happens frequently enough, +the apparent backlog will cause TCP to begin "congestion control" +unnecessarily, culminating in permanently decreased throughput. + +Fixes: d7c0ef36bde03 ("ibmvnic: Free and re-allocate scrqs when tx/rx scrqs change") +Tested-by: Nick Child +Reviewed-by: Brian King +Signed-off-by: Rick Lindsley +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/ibm/ibmvnic.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c +index 28344c3dfea1..4a070724a8fb 100644 +--- a/drivers/net/ethernet/ibm/ibmvnic.c ++++ b/drivers/net/ethernet/ibm/ibmvnic.c +@@ -5585,6 +5585,15 @@ static int ibmvnic_reset_init(struct ibmvnic_adapter *adapter, bool reset) + release_sub_crqs(adapter, 0); + rc = init_sub_crqs(adapter); + } else { ++ /* no need to reinitialize completely, but we do ++ * need to clean up transmits that were in flight ++ * when we processed the reset. Failure to do so ++ * will confound the upper layer, usually TCP, by ++ * creating the illusion of transmits that are ++ * awaiting completion. ++ */ ++ clean_tx_pools(adapter); ++ + rc = reset_sub_crq_queues(adapter); + } + } else { +-- +2.35.1 + diff --git a/queue-5.15/pinctrl-sunxi-a83t-fix-nand-function-name-for-some-p.patch b/queue-5.15/pinctrl-sunxi-a83t-fix-nand-function-name-for-some-p.patch new file mode 100644 index 00000000000..23c8d50a9d5 --- /dev/null +++ b/queue-5.15/pinctrl-sunxi-a83t-fix-nand-function-name-for-some-p.patch @@ -0,0 +1,61 @@ +From ecf6a2ce9cdb4b3160e0bc2e8f7ab9dd76ab8313 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 25 May 2022 21:49:56 -0500 +Subject: pinctrl: sunxi: a83t: Fix NAND function name for some pins + +From: Samuel Holland + +[ Upstream commit aaefa29270d9551b604165a08406543efa9d16f5 ] + +The other NAND pins on Port C use the "nand0" function name. +"nand0" also matches all of the other Allwinner SoCs. + +Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller support") +Signed-off-by: Samuel Holland +Acked-by: Jernej Skrabec +Link: https://lore.kernel.org/r/20220526024956.49500-1-samuel@sholland.org +Signed-off-by: Linus Walleij +Signed-off-by: Sasha Levin +--- + drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c +index 4ada80317a3b..b5c1a8f363f3 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c +@@ -158,26 +158,26 @@ static const struct sunxi_desc_pin sun8i_a83t_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), +- SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */ ++ SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), +- SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */ ++ SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), +- SUNXI_FUNCTION(0x2, "nand"), /* DQS */ ++ SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ + SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), +- SUNXI_FUNCTION(0x2, "nand")), /* CE2 */ ++ SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), +- SUNXI_FUNCTION(0x2, "nand")), /* CE3 */ ++ SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), +-- +2.35.1 + diff --git a/queue-5.15/pinctrl-sunxi-sunxi_pconf_set-use-correct-offset.patch b/queue-5.15/pinctrl-sunxi-sunxi_pconf_set-use-correct-offset.patch new file mode 100644 index 00000000000..1d93ef34ed4 --- /dev/null +++ b/queue-5.15/pinctrl-sunxi-sunxi_pconf_set-use-correct-offset.patch @@ -0,0 +1,40 @@ +From 92f140bb45d6809852aaac6be98470fca81244aa Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 25 May 2022 22:04:25 +0300 +Subject: pinctrl: sunxi: sunxi_pconf_set: use correct offset + +From: Andrei Lalaev + +[ Upstream commit cd4c1e65a32afd003b08ad4aafe1e4d3e4e8e61b ] + +Some Allwinner SoCs have 2 pinctrls (PIO and R_PIO). +Previous implementation used absolute pin numbering and it was incorrect +for R_PIO pinctrl. +It's necessary to take into account the base pin number. + +Fixes: 90be64e27621 ("pinctrl: sunxi: implement pin_config_set") +Signed-off-by: Andrei Lalaev +Reviewed-by: Samuel Holland +Link: https://lore.kernel.org/r/20220525190423.410609-1-andrey.lalaev@gmail.com +Signed-off-by: Linus Walleij +Signed-off-by: Sasha Levin +--- + drivers/pinctrl/sunxi/pinctrl-sunxi.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c +index ce3f9ea41511..1431ab21aca6 100644 +--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c ++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c +@@ -544,6 +544,8 @@ static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin, + struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + int i; + ++ pin -= pctl->desc->pin_base; ++ + for (i = 0; i < num_configs; i++) { + enum pin_config_param param; + unsigned long flags; +-- +2.35.1 + diff --git a/queue-5.15/r8169-fix-accessing-unset-transport-header.patch b/queue-5.15/r8169-fix-accessing-unset-transport-header.patch new file mode 100644 index 00000000000..edcc901692c --- /dev/null +++ b/queue-5.15/r8169-fix-accessing-unset-transport-header.patch @@ -0,0 +1,89 @@ +From 2d642f4c6548e06d5cee3254caa63ca7ee57a51f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 5 Jul 2022 21:15:22 +0200 +Subject: r8169: fix accessing unset transport header + +From: Heiner Kallweit + +[ Upstream commit faa4e04e5e140a6d02260289a8fba8fd8d7a3003 ] + +66e4c8d95008 ("net: warn if transport header was not set") added +a check that triggers a warning in r8169, see [0]. + +The commit referenced in the Fixes tag refers to the change from +which the patch applies cleanly, there's nothing wrong with this +commit. It seems the actual issue (not bug, because the warning +is harmless here) was introduced with bdfa4ed68187 +("r8169: use Giant Send"). + +[0] https://bugzilla.kernel.org/show_bug.cgi?id=216157 + +Fixes: 8d520b4de3ed ("r8169: work around RTL8125 UDP hw bug") +Reported-by: Erhard F. +Tested-by: Erhard F. +Signed-off-by: Heiner Kallweit +Link: https://lore.kernel.org/r/1b2c2b29-3dc0-f7b6-5694-97ec526d51a0@gmail.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/realtek/r8169_main.c | 10 ++++------ + 1 file changed, 4 insertions(+), 6 deletions(-) + +diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c +index 2918947dd57c..2af4c76bcf02 100644 +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -4177,7 +4177,6 @@ static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) + static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, + struct sk_buff *skb, u32 *opts) + { +- u32 transport_offset = (u32)skb_transport_offset(skb); + struct skb_shared_info *shinfo = skb_shinfo(skb); + u32 mss = shinfo->gso_size; + +@@ -4194,7 +4193,7 @@ static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, + WARN_ON_ONCE(1); + } + +- opts[0] |= transport_offset << GTTCPHO_SHIFT; ++ opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; + opts[1] |= mss << TD1_MSS_SHIFT; + } else if (skb->ip_summed == CHECKSUM_PARTIAL) { + u8 ip_protocol; +@@ -4222,7 +4221,7 @@ static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, + else + WARN_ON_ONCE(1); + +- opts[1] |= transport_offset << TCPHO_SHIFT; ++ opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; + } else { + unsigned int padto = rtl_quirk_packet_padto(tp, skb); + +@@ -4389,14 +4388,13 @@ static netdev_features_t rtl8169_features_check(struct sk_buff *skb, + struct net_device *dev, + netdev_features_t features) + { +- int transport_offset = skb_transport_offset(skb); + struct rtl8169_private *tp = netdev_priv(dev); + + if (skb_is_gso(skb)) { + if (tp->mac_version == RTL_GIGA_MAC_VER_34) + features = rtl8168evl_fix_tso(skb, features); + +- if (transport_offset > GTTCPHO_MAX && ++ if (skb_transport_offset(skb) > GTTCPHO_MAX && + rtl_chip_supports_csum_v2(tp)) + features &= ~NETIF_F_ALL_TSO; + } else if (skb->ip_summed == CHECKSUM_PARTIAL) { +@@ -4407,7 +4405,7 @@ static netdev_features_t rtl8169_features_check(struct sk_buff *skb, + if (rtl_quirk_packet_padto(tp, skb)) + features &= ~NETIF_F_CSUM_MASK; + +- if (transport_offset > TCPHO_MAX && ++ if (skb_transport_offset(skb) > TCPHO_MAX && + rtl_chip_supports_csum_v2(tp)) + features &= ~NETIF_F_CSUM_MASK; + } +-- +2.35.1 + diff --git a/queue-5.15/selftests-forwarding-fix-error-message-in-learning_t.patch b/queue-5.15/selftests-forwarding-fix-error-message-in-learning_t.patch new file mode 100644 index 00000000000..5de227bb6f2 --- /dev/null +++ b/queue-5.15/selftests-forwarding-fix-error-message-in-learning_t.patch @@ -0,0 +1,38 @@ +From 2f46c749345a92a65cc1e0448795ff5046688b3e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 3 Jul 2022 10:36:26 +0300 +Subject: selftests: forwarding: fix error message in learning_test + +From: Vladimir Oltean + +[ Upstream commit 83844aacab2015da1dba1df0cc61fc4b4c4e8076 ] + +When packets are not received, they aren't received on $host1_if, so the +message talking about the second host not receiving them is incorrect. +Fix it. + +Fixes: d4deb01467ec ("selftests: forwarding: Add a test for FDB learning") +Signed-off-by: Vladimir Oltean +Reviewed-by: Ido Schimmel +Signed-off-by: Paolo Abeni +Signed-off-by: Sasha Levin +--- + tools/testing/selftests/net/forwarding/lib.sh | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/tools/testing/selftests/net/forwarding/lib.sh b/tools/testing/selftests/net/forwarding/lib.sh +index 0db6ea8d7e05..c9507df9c05b 100644 +--- a/tools/testing/selftests/net/forwarding/lib.sh ++++ b/tools/testing/selftests/net/forwarding/lib.sh +@@ -1160,7 +1160,7 @@ learning_test() + tc -j -s filter show dev $host1_if ingress \ + | jq -e ".[] | select(.options.handle == 101) \ + | select(.options.actions[0].stats.packets == 1)" &> /dev/null +- check_fail $? "Packet reached second host when should not" ++ check_fail $? "Packet reached first host when should not" + + $MZ $host1_if -c 1 -p 64 -a $mac -t ip -q + sleep 1 +-- +2.35.1 + diff --git a/queue-5.15/selftests-forwarding-fix-flood_unicast_test-when-h2-.patch b/queue-5.15/selftests-forwarding-fix-flood_unicast_test-when-h2-.patch new file mode 100644 index 00000000000..b95a5ae82fe --- /dev/null +++ b/queue-5.15/selftests-forwarding-fix-flood_unicast_test-when-h2-.patch @@ -0,0 +1,61 @@ +From 097ac2357c2d343c7f833e3c8165620abf78cfac Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 3 Jul 2022 10:36:24 +0300 +Subject: selftests: forwarding: fix flood_unicast_test when h2 supports + IFF_UNICAST_FLT + +From: Vladimir Oltean + +[ Upstream commit b8e629b05f5d23f9649c901bef09fab8b0c2e4b9 ] + +As mentioned in the blamed commit, flood_unicast_test() works by +checking the match count on a tc filter placed on the receiving +interface. + +But the second host interface (host2_if) has no interest in receiving a +packet with MAC DA de:ad:be:ef:13:37, so its RX filter drops it even +before the ingress tc filter gets to be executed. So we will incorrectly +get the message "Packet was not flooded when should", when in fact, the +packet was flooded as expected but dropped due to an unrelated reason, +at some other layer on the receiving side. + +Force h2 to accept this packet by temporarily placing it in promiscuous +mode. Alternatively we could either deliver to its MAC address or use +tcpdump_start, but this has the fewest complications. + +This fixes the "flooding" test from bridge_vlan_aware.sh and +bridge_vlan_unaware.sh, which calls flood_test from the lib. + +Fixes: 236dd50bf67a ("selftests: forwarding: Add a test for flooded traffic") +Signed-off-by: Vladimir Oltean +Reviewed-by: Ido Schimmel +Tested-by: Ido Schimmel +Signed-off-by: Paolo Abeni +Signed-off-by: Sasha Levin +--- + tools/testing/selftests/net/forwarding/lib.sh | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/tools/testing/selftests/net/forwarding/lib.sh b/tools/testing/selftests/net/forwarding/lib.sh +index 92087d423bcf..8a9c55fe841a 100644 +--- a/tools/testing/selftests/net/forwarding/lib.sh ++++ b/tools/testing/selftests/net/forwarding/lib.sh +@@ -1215,6 +1215,7 @@ flood_test_do() + + # Add an ACL on `host2_if` which will tell us whether the packet + # was flooded to it or not. ++ ip link set $host2_if promisc on + tc qdisc add dev $host2_if ingress + tc filter add dev $host2_if ingress protocol ip pref 1 handle 101 \ + flower dst_mac $mac action drop +@@ -1232,6 +1233,7 @@ flood_test_do() + + tc filter del dev $host2_if ingress protocol ip pref 1 handle 101 flower + tc qdisc del dev $host2_if ingress ++ ip link set $host2_if promisc off + + return $err + } +-- +2.35.1 + diff --git a/queue-5.15/selftests-forwarding-fix-learning_test-when-h1-suppo.patch b/queue-5.15/selftests-forwarding-fix-learning_test-when-h1-suppo.patch new file mode 100644 index 00000000000..72a755a9405 --- /dev/null +++ b/queue-5.15/selftests-forwarding-fix-learning_test-when-h1-suppo.patch @@ -0,0 +1,50 @@ +From aaa29b2bb0bf78f928f2c4ed589a92a59b0eaca1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 3 Jul 2022 10:36:25 +0300 +Subject: selftests: forwarding: fix learning_test when h1 supports + IFF_UNICAST_FLT + +From: Vladimir Oltean + +[ Upstream commit 1a635d3e1c80626237fdae47a5545b6655d8d81c ] + +The first host interface has by default no interest in receiving packets +MAC DA de:ad:be:ef:13:37, so it might drop them before they hit the tc +filter and this might confuse the selftest. + +Enable promiscuous mode such that the filter properly counts received +packets. + +Fixes: d4deb01467ec ("selftests: forwarding: Add a test for FDB learning") +Signed-off-by: Vladimir Oltean +Reviewed-by: Ido Schimmel +Tested-by: Ido Schimmel +Signed-off-by: Paolo Abeni +Signed-off-by: Sasha Levin +--- + tools/testing/selftests/net/forwarding/lib.sh | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/tools/testing/selftests/net/forwarding/lib.sh b/tools/testing/selftests/net/forwarding/lib.sh +index 8a9c55fe841a..0db6ea8d7e05 100644 +--- a/tools/testing/selftests/net/forwarding/lib.sh ++++ b/tools/testing/selftests/net/forwarding/lib.sh +@@ -1149,6 +1149,7 @@ learning_test() + # FDB entry was installed. + bridge link set dev $br_port1 flood off + ++ ip link set $host1_if promisc on + tc qdisc add dev $host1_if ingress + tc filter add dev $host1_if ingress protocol ip pref 1 handle 101 \ + flower dst_mac $mac action drop +@@ -1198,6 +1199,7 @@ learning_test() + + tc filter del dev $host1_if ingress protocol ip pref 1 handle 101 flower + tc qdisc del dev $host1_if ingress ++ ip link set $host1_if promisc off + + bridge link set dev $br_port1 flood on + +-- +2.35.1 + diff --git a/queue-5.15/series b/queue-5.15/series index 8588ad2fbf2..abfaee94095 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -176,3 +176,41 @@ btrfs-fix-error-pointer-dereference-in-btrfs_ioctl_rm_dev_v2.patch virtio-blk-modify-the-value-type-of-num-in-virtio_queue_rq.patch btrfs-fix-use-of-uninitialized-variable-at-rm-device-ioctl.patch tty-n_gsm-fix-encoding-of-command-response-bit.patch +arm-meson-fix-refcount-leak-in-meson_smp_prepare_cpu.patch +pinctrl-sunxi-a83t-fix-nand-function-name-for-some-p.patch +asoc-rt711-add-endianness-flag-in-snd_soc_component_.patch +asoc-rt711-sdca-add-endianness-flag-in-snd_soc_compo.patch +asoc-codecs-rt700-rt711-rt711-sdca-resume-bus-codec-.patch +arm64-dts-qcom-msm8994-fix-cpu6-7-reg-values.patch +arm64-dts-qcom-sdm845-use-dispcc-ahb-clock-for-mdss-.patch +arm-mxs_defconfig-enable-the-framebuffer.patch +arm64-dts-imx8mp-evk-correct-mmc-pad-settings.patch +arm64-dts-imx8mp-evk-correct-the-uart2-pinctl-value.patch +arm64-dts-imx8mp-evk-correct-gpio-led-pad-settings.patch +arm64-dts-imx8mp-evk-correct-vbus-pad-settings.patch +arm64-dts-imx8mp-evk-correct-eqos-pad-settings.patch +arm64-dts-imx8mp-evk-correct-i2c1-pad-settings.patch +arm64-dts-imx8mp-evk-correct-i2c3-pad-settings.patch +arm64-dts-imx8mp-phyboard-pollux-rdk-correct-uart-pa.patch +arm64-dts-imx8mp-phyboard-pollux-rdk-correct-eqos-pa.patch +arm64-dts-imx8mp-phyboard-pollux-rdk-correct-i2c2-mm.patch +pinctrl-sunxi-sunxi_pconf_set-use-correct-offset.patch +arm64-dts-qcom-msm8992-fix-vdd_lvs1_2-supply-typo.patch +arm-at91-pm-use-proper-compatible-for-sama5d2-s-rtc.patch +arm-at91-pm-use-proper-compatibles-for-sam9x60-s-rtc.patch +arm-at91-pm-use-proper-compatibles-for-sama7g5-s-rtc.patch +arm-dts-at91-sam9x60ek-fix-eeprom-compatible-and-siz.patch +arm-dts-at91-sama5d2_icp-fix-eeprom-compatibles.patch +arm-at91-fix-soc-detection-for-sam9x60-sips.patch +xsk-clear-page-contiguity-bit-when-unmapping-pool.patch +i2c-piix4-fix-a-memory-leak-in-the-efch-mmio-support.patch +i40e-fix-dropped-jumbo-frames-statistics.patch +i40e-fix-vf-s-mac-address-change-on-vm.patch +arm-dts-stm32-use-usbphyc-ck_usbo_48m-as-usbh-ohci-c.patch +arm-dts-stm32-add-missing-usbh-clock-and-fix-clk-ord.patch +ibmvnic-properly-dispose-of-all-skbs-during-a-failov.patch +selftests-forwarding-fix-flood_unicast_test-when-h2-.patch +selftests-forwarding-fix-learning_test-when-h1-suppo.patch +selftests-forwarding-fix-error-message-in-learning_t.patch +r8169-fix-accessing-unset-transport-header.patch +i2c-cadence-unregister-the-clk-notifier-in-error-pat.patch diff --git a/queue-5.15/xsk-clear-page-contiguity-bit-when-unmapping-pool.patch b/queue-5.15/xsk-clear-page-contiguity-bit-when-unmapping-pool.patch new file mode 100644 index 00000000000..e0d56051fd8 --- /dev/null +++ b/queue-5.15/xsk-clear-page-contiguity-bit-when-unmapping-pool.patch @@ -0,0 +1,41 @@ +From 6c1e11162b6eea83bb742ede40988fb4aee623a0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Jun 2022 12:18:48 +0300 +Subject: xsk: Clear page contiguity bit when unmapping pool + +From: Ivan Malov + +[ Upstream commit 512d1999b8e94a5d43fba3afc73e774849674742 ] + +When a XSK pool gets mapped, xp_check_dma_contiguity() adds bit 0x1 +to pages' DMA addresses that go in ascending order and at 4K stride. + +The problem is that the bit does not get cleared before doing unmap. +As a result, a lot of warnings from iommu_dma_unmap_page() are seen +in dmesg, which indicates that lookups by iommu_iova_to_phys() fail. + +Fixes: 2b43470add8c ("xsk: Introduce AF_XDP buffer allocation API") +Signed-off-by: Ivan Malov +Signed-off-by: Daniel Borkmann +Acked-by: Magnus Karlsson +Link: https://lore.kernel.org/bpf/20220628091848.534803-1-ivan.malov@oktetlabs.ru +Signed-off-by: Sasha Levin +--- + net/xdp/xsk_buff_pool.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/net/xdp/xsk_buff_pool.c b/net/xdp/xsk_buff_pool.c +index fc7fbfc1e586..ccedbbd27692 100644 +--- a/net/xdp/xsk_buff_pool.c ++++ b/net/xdp/xsk_buff_pool.c +@@ -326,6 +326,7 @@ static void __xp_dma_unmap(struct xsk_dma_map *dma_map, unsigned long attrs) + for (i = 0; i < dma_map->dma_pages_cnt; i++) { + dma = &dma_map->dma_pages[i]; + if (*dma) { ++ *dma &= ~XSK_NEXT_PG_CONTIG_MASK; + dma_unmap_page_attrs(dma_map->dev, *dma, PAGE_SIZE, + DMA_BIDIRECTIONAL, attrs); + *dma = 0; +-- +2.35.1 +