From: Pan Li <pan2.li@intel.com>
Date: Thu, 31 Jul 2025 04:32:24 +0000 (+0800)
Subject: RISC-V: Fix scalar code-gen of unsigned SAT_MUL
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=01a784e7c5e724be3ff5ab663eb288d3ed66100b;p=thirdparty%2Fgcc.git

RISC-V: Fix scalar code-gen of unsigned SAT_MUL

The previous code-gen of scalar unsigned SAT_MUL, aka usmul.
Leverage the mulhs by mistake, it should be mulhu for the
hight bit result of mul.  Thus, this patch would like to make
it correct.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_expand_xmode_usmul): Take
	umulhu for high bits mul result.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c: Add mulhu
	asm check.
	* gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
---

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0a9fcef3702..e0d8904c1bf 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -13867,9 +13867,9 @@ riscv_expand_xmode_usmul (rtx dest, rtx x, rtx y)
   riscv_emit_binary (MULT, mul, x, y);
 
   if (TARGET_64BIT)
-    emit_insn (gen_usmuldi3_highpart (mulhu, x, y));
+    emit_insn (gen_umuldi3_highpart (mulhu, x, y));
   else
-    emit_insn (gen_usmulsi3_highpart (mulhu, x, y));
+    emit_insn (gen_umulsi3_highpart (mulhu, x, y));
 
   riscv_emit_binary (NE, overflow_p, mulhu, CONST0_RTX (Xmode));
   riscv_emit_unary (NEG, overflow_p, overflow_p);
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c
index 8d5449bf349..fa3758a2f54 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c
@@ -9,3 +9,5 @@
 DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT)
 
 /* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
+/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */
+/* { dg-final { scan-assembler-times "mulhu" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c
index d8a01d1a06f..b1bf4fae968 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c
@@ -10,3 +10,4 @@ DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT)
 
 /* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
 /* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */
+/* { dg-final { scan-assembler-times "mulhu" 1 } } */