From: Sasha Levin Date: Tue, 2 Jul 2024 10:20:08 +0000 (-0400) Subject: Fixes for 6.6 X-Git-Tag: v4.19.317~36^2~5 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=01a9583a99555071bcabd406e518e0973a8aae87;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 6.6 Signed-off-by: Sasha Levin --- diff --git a/queue-6.6/arm-dts-rockchip-rk3066a-add-sound-dai-cells-to-hdmi.patch b/queue-6.6/arm-dts-rockchip-rk3066a-add-sound-dai-cells-to-hdmi.patch new file mode 100644 index 00000000000..b3310c173da --- /dev/null +++ b/queue-6.6/arm-dts-rockchip-rk3066a-add-sound-dai-cells-to-hdmi.patch @@ -0,0 +1,37 @@ +From 11492e735b72450e70e0d5f7179a084aaaf202be Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 13 Jun 2024 20:08:10 +0200 +Subject: ARM: dts: rockchip: rk3066a: add #sound-dai-cells to hdmi node + +From: Johan Jonker + +[ Upstream commit cca46f811d0000c1522a5e18ea48c27a15e45c05 ] + +'#sound-dai-cells' is required to properly interpret +the list of DAI specified in the 'sound-dai' property, +so add them to the 'hdmi' node for 'rk3066a.dtsi'. + +Fixes: fadc78062477 ("ARM: dts: rockchip: add rk3066 hdmi nodes") +Signed-off-by: Johan Jonker +Link: https://lore.kernel.org/r/8b229dcc-94e4-4bbc-9efc-9d5ddd694532@gmail.com +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/rockchip/rk3066a.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/boot/dts/rockchip/rk3066a.dtsi b/arch/arm/boot/dts/rockchip/rk3066a.dtsi +index de9915d946f74..b98d5e357baf3 100644 +--- a/arch/arm/boot/dts/rockchip/rk3066a.dtsi ++++ b/arch/arm/boot/dts/rockchip/rk3066a.dtsi +@@ -123,6 +123,7 @@ + pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; + power-domains = <&power RK3066_PD_VIO>; + rockchip,grf = <&grf>; ++ #sound-dai-cells = <0>; + status = "disabled"; + + ports { +-- +2.43.0 + diff --git a/queue-6.6/arm64-dts-rockchip-add-sound-dai-cells-for-rk3368.patch b/queue-6.6/arm64-dts-rockchip-add-sound-dai-cells-for-rk3368.patch new file mode 100644 index 00000000000..67c7dcb09b9 --- /dev/null +++ b/queue-6.6/arm64-dts-rockchip-add-sound-dai-cells-for-rk3368.patch @@ -0,0 +1,52 @@ +From 8222856542db9e6e21fc49cdc59399f95310256e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 23 Jun 2024 11:01:15 +0200 +Subject: arm64: dts: rockchip: Add sound-dai-cells for RK3368 + +From: Alex Bee + +[ Upstream commit 8d7ec44aa5d1eb94a30319074762a1740440cdc8 ] + +Add the missing #sound-dai-cells for RK3368's I2S and S/PDIF controllers. + +Fixes: f7d89dfe1e31 ("arm64: dts: rockchip: add i2s nodes support for RK3368 SoCs") +Fixes: 0328d68ea76d ("arm64: dts: rockchip: add rk3368 spdif node") +Signed-off-by: Alex Bee +Link: https://lore.kernel.org/r/20240623090116.670607-4-knaerzche@gmail.com +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/rockchip/rk3368.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi +index a4c5aaf1f4579..cac58ad951b2e 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi +@@ -790,6 +790,7 @@ + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx>; ++ #sound-dai-cells = <0>; + status = "disabled"; + }; + +@@ -801,6 +802,7 @@ + clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>; + dmas = <&dmac_bus 6>, <&dmac_bus 7>; + dma-names = "tx", "rx"; ++ #sound-dai-cells = <0>; + status = "disabled"; + }; + +@@ -814,6 +816,7 @@ + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_bus>; ++ #sound-dai-cells = <0>; + status = "disabled"; + }; + +-- +2.43.0 + diff --git a/queue-6.6/arm64-dts-rockchip-fix-pmic-interrupt-pin-on-rock-pi.patch b/queue-6.6/arm64-dts-rockchip-fix-pmic-interrupt-pin-on-rock-pi.patch new file mode 100644 index 00000000000..04bf3881c69 --- /dev/null +++ b/queue-6.6/arm64-dts-rockchip-fix-pmic-interrupt-pin-on-rock-pi.patch @@ -0,0 +1,39 @@ +From ec4596f9c29de12006312732f18c87ed1f14a082 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 19 Jun 2024 14:00:46 +0900 +Subject: arm64: dts: rockchip: fix PMIC interrupt pin on ROCK Pi E + +From: FUKAUMI Naoki + +[ Upstream commit 02afd3d5b9fa4ffed284c0f7e7bec609097804fc ] + +use GPIO0_A2 as interrupt pin for PMIC. GPIO2_A6 was used for +pre-production board. + +Fixes: b918e81f2145 ("arm64: dts: rockchip: rk3328: Add Radxa ROCK Pi E") +Signed-off-by: FUKAUMI Naoki +Link: https://lore.kernel.org/r/20240619050047.1217-1-naoki@radxa.com +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts +index 018a3a5075c72..d9905a08c6ce8 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts +@@ -186,8 +186,8 @@ + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; +- interrupt-parent = <&gpio2>; +- interrupts = <6 IRQ_TYPE_LEVEL_LOW>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; +-- +2.43.0 + diff --git a/queue-6.6/arm64-dts-rockchip-fix-sd-nand-and-emmc-init-on-rk33.patch b/queue-6.6/arm64-dts-rockchip-fix-sd-nand-and-emmc-init-on-rk33.patch new file mode 100644 index 00000000000..355510fc348 --- /dev/null +++ b/queue-6.6/arm64-dts-rockchip-fix-sd-nand-and-emmc-init-on-rk33.patch @@ -0,0 +1,58 @@ +From 51b08da0ddd11bfb576b3d78934356048a751dcf Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 21 May 2024 21:10:06 +0000 +Subject: arm64: dts: rockchip: Fix SD NAND and eMMC init on rk3308-rock-pi-s + +From: Jonas Karlman + +[ Upstream commit 1fb98c855ccd7bc7f50c7a9626fbb8440454760b ] + +Radxa ROCK Pi S have optional onboard SD NAND on board revision v1.1, +v1.2 and v1.3, revision v1.5 changed to use optional onboard eMMC. + +The optional SD NAND typically fails to initialize: + + mmc_host mmc0: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0) + mmc0: error -110 whilst initialising SD card + mmc_host mmc0: Bus speed (slot 0) = 300000Hz (slot req 300000Hz, actual 300000HZ div = 0) + mmc0: error -110 whilst initialising SD card + mmc_host mmc0: Bus speed (slot 0) = 200000Hz (slot req 200000Hz, actual 200000HZ div = 0) + mmc0: error -110 whilst initialising SD card + mmc_host mmc0: Bus speed (slot 0) = 100000Hz (slot req 100000Hz, actual 100000HZ div = 0) + mmc0: error -110 whilst initialising SD card + +Add pinctrl and cap-sd-highspeed to fix SD NAND initialization. Also +drop bus-width and mmc-hs200-1_8v to fix eMMC initialization on the new +v1.5 board revision, only 3v3 signal voltage is used. + +Fixes: 2e04c25b1320 ("arm64: dts: rockchip: add ROCK Pi S DTS support") +Signed-off-by: Jonas Karlman +Link: https://lore.kernel.org/r/20240521211029.1236094-4-jonas@kwiboo.se +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +index e9810d2f04071..40b2f27aa6312 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +@@ -126,10 +126,12 @@ + }; + + &emmc { +- bus-width = <4>; + cap-mmc-highspeed; +- mmc-hs200-1_8v; ++ cap-sd-highspeed; ++ no-sdio; + non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + vmmc-supply = <&vcc_io>; + status = "okay"; + }; +-- +2.43.0 + diff --git a/queue-6.6/arm64-dts-rockchip-fix-the-value-of-dlg-jack-det-rat.patch b/queue-6.6/arm64-dts-rockchip-fix-the-value-of-dlg-jack-det-rat.patch new file mode 100644 index 00000000000..edf74c38a3d --- /dev/null +++ b/queue-6.6/arm64-dts-rockchip-fix-the-value-of-dlg-jack-det-rat.patch @@ -0,0 +1,39 @@ +From 2e1e39f650c0cd26c09b5893fa4c176561b901e0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 13 Jun 2024 11:58:55 +0000 +Subject: arm64: dts: rockchip: Fix the value of `dlg,jack-det-rate` mismatch + on rk3399-gru + +From: Hsin-Te Yuan + +[ Upstream commit a500c0b4b589ae6fb79140c9d96bd5cd31393d41 ] + +According to Documentation/devicetree/bindings/sound/dialog,da7219.yaml, +the value of `dlg,jack-det-rate` property should be "32_64" instead of +"32ms_64ms". + +Fixes: dc0ff0fa3a9b ("ASoC: da7219: Add Jack insertion detection polarity") +Signed-off-by: Hsin-Te Yuan +Link: https://lore.kernel.org/r/20240613-jack-rate-v2-2-ebc5f9f37931@chromium.org +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +index 789fd0dcc88ba..3cd63d1e8f15b 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +@@ -450,7 +450,7 @@ ap_i2c_audio: &i2c8 { + dlg,btn-cfg = <50>; + dlg,mic-det-thr = <500>; + dlg,jack-ins-deb = <20>; +- dlg,jack-det-rate = "32ms_64ms"; ++ dlg,jack-det-rate = "32_64"; + dlg,jack-rem-deb = <1>; + + dlg,a-d-btn-thr = <0xa>; +-- +2.43.0 + diff --git a/queue-6.6/arm64-dts-rockchip-make-poweroff-8-work-on-radxa-roc.patch b/queue-6.6/arm64-dts-rockchip-make-poweroff-8-work-on-radxa-roc.patch new file mode 100644 index 00000000000..a2b87c71a1a --- /dev/null +++ b/queue-6.6/arm64-dts-rockchip-make-poweroff-8-work-on-radxa-roc.patch @@ -0,0 +1,37 @@ +From 6b8a3dc51ac88415449689ec10dcd2213b352836 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 12 Jun 2024 12:35:23 +0900 +Subject: arm64: dts: rockchip: make poweroff(8) work on Radxa ROCK 5A + +From: FUKAUMI Naoki + +[ Upstream commit d05f7aff7ac23884ed9103a876325047ff9049aa ] + +Designate the RK806 PMIC on the Radxa ROCK 5A as the system power +controller, so the board shuts down properly on poweroff(8). + +Fixes: 75fdcbc8f4c1 ("arm64: dts: rockchip: add PMIC to rock-5a") +Reviewed-by: Dragan Simic +Signed-off-by: FUKAUMI Naoki +Link: https://lore.kernel.org/r/20240612033523.37166-1-naoki@radxa.com +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +index 8347adcbd0030..68763714f7f7b 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -390,6 +390,7 @@ + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; ++ system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; +-- +2.43.0 + diff --git a/queue-6.6/arm64-dts-rockchip-rename-led-related-pinctrl-nodes-.patch b/queue-6.6/arm64-dts-rockchip-rename-led-related-pinctrl-nodes-.patch new file mode 100644 index 00000000000..8c167528ef6 --- /dev/null +++ b/queue-6.6/arm64-dts-rockchip-rename-led-related-pinctrl-nodes-.patch @@ -0,0 +1,83 @@ +From 199c435bf0fd8642aec92d9e737f551003542783 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 21 May 2024 21:10:09 +0000 +Subject: arm64: dts: rockchip: Rename LED related pinctrl nodes on + rk3308-rock-pi-s + +From: Jonas Karlman + +[ Upstream commit d2a52f678883fe4bc00bca89366b1ba504750abf ] + +The nodename, -gpio, of referenced pinctrl nodes for the two LEDs +on the ROCK Pi S cause DT schema validation error: + + leds: green-led-gpio: {'rockchip,pins': [[0, 6, 0, 90]], 'phandle': [[98]]} is not of type 'array' + from schema $id: http://devicetree.org/schemas/gpio/gpio-consumer.yaml# + leds: heartbeat-led-gpio: {'rockchip,pins': [[0, 5, 0, 90]], 'phandle': [[99]]} is not of type 'array' + from schema $id: http://devicetree.org/schemas/gpio/gpio-consumer.yaml# + +Rename the pinctrl nodes and symbols to pass DT schema validation, also +extend LED nodes with information about color and function. + +Fixes: 2e04c25b1320 ("arm64: dts: rockchip: add ROCK Pi S DTS support") +Signed-off-by: Jonas Karlman +Link: https://lore.kernel.org/r/20240521211029.1236094-7-jonas@kwiboo.se +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +--- + arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts | 12 +++++++++--- + 1 file changed, 9 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +index 40b2f27aa6312..4f6541262ab84 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts +@@ -5,6 +5,8 @@ + */ + + /dts-v1/; ++ ++#include + #include "rk3308.dtsi" + + / { +@@ -24,17 +26,21 @@ + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; +- pinctrl-0 = <&green_led_gio>, <&heartbeat_led_gpio>; ++ pinctrl-0 = <&green_led>, <&heartbeat_led>; + + green-led { ++ color = ; + default-state = "on"; ++ function = LED_FUNCTION_POWER; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + label = "rockpis:green:power"; + linux,default-trigger = "default-on"; + }; + + blue-led { ++ color = ; + default-state = "on"; ++ function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + label = "rockpis:blue:user"; + linux,default-trigger = "heartbeat"; +@@ -154,11 +160,11 @@ + pinctrl-0 = <&rtc_32k>; + + leds { +- green_led_gio: green-led-gpio { ++ green_led: green-led { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + +- heartbeat_led_gpio: heartbeat-led-gpio { ++ heartbeat_led: heartbeat-led { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +-- +2.43.0 + diff --git a/queue-6.6/cxl-region-avoid-null-pointer-dereference-in-region-.patch b/queue-6.6/cxl-region-avoid-null-pointer-dereference-in-region-.patch new file mode 100644 index 00000000000..6c0c5c9dbfc --- /dev/null +++ b/queue-6.6/cxl-region-avoid-null-pointer-dereference-in-region-.patch @@ -0,0 +1,85 @@ +From 92ac56832323fcd38d82d888e8da21ba207fd680 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 3 Jun 2024 17:36:09 -0700 +Subject: cxl/region: Avoid null pointer dereference in region lookup + +From: Alison Schofield + +[ Upstream commit 285f2a08841432fc3e498b1cd00cce5216cdf189 ] + +cxl_dpa_to_region() looks up a region based on a memdev and DPA. +It wrongly assumes an endpoint found mapping the DPA is also of +a fully assembled region. When not true it leads to a null pointer +dereference looking up the region name. + +This appears during testing of region lookup after a failure to +assemble a BIOS defined region or if the lookup raced with the +assembly of the BIOS defined region. + +Failure to clean up BIOS defined regions that fail assembly is an +issue in itself and a fix to that problem will alleviate some of +the impact. It will not alleviate the race condition so let's harden +this path. + +The behavior change is that the kernel oops due to a null pointer +dereference is replaced with a dev_dbg() message noting that an +endpoint was mapped. + +Additional comments are added so that future users of this function +can more clearly understand what it provides. + +Fixes: 0a105ab28a4d ("cxl/memdev: Warn of poison inject or clear to a mapped region") +Signed-off-by: Alison Schofield +Reviewed-by: Jonathan Cameron +Link: https://patch.msgid.link/20240604003609.202682-1-alison.schofield@intel.com +Signed-off-by: Dave Jiang +Signed-off-by: Sasha Levin +--- + drivers/cxl/core/region.c | 19 +++++++++++++++---- + 1 file changed, 15 insertions(+), 4 deletions(-) + +diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c +index d2ce309434654..0d59af19ecee7 100644 +--- a/drivers/cxl/core/region.c ++++ b/drivers/cxl/core/region.c +@@ -2518,22 +2518,33 @@ static int __cxl_dpa_to_region(struct device *dev, void *arg) + { + struct cxl_dpa_to_region_context *ctx = arg; + struct cxl_endpoint_decoder *cxled; ++ struct cxl_region *cxlr; + u64 dpa = ctx->dpa; + + if (!is_endpoint_decoder(dev)) + return 0; + + cxled = to_cxl_endpoint_decoder(dev); +- if (!cxled->dpa_res || !resource_size(cxled->dpa_res)) ++ if (!cxled || !cxled->dpa_res || !resource_size(cxled->dpa_res)) + return 0; + + if (dpa > cxled->dpa_res->end || dpa < cxled->dpa_res->start) + return 0; + +- dev_dbg(dev, "dpa:0x%llx mapped in region:%s\n", dpa, +- dev_name(&cxled->cxld.region->dev)); ++ /* ++ * Stop the region search (return 1) when an endpoint mapping is ++ * found. The region may not be fully constructed so offering ++ * the cxlr in the context structure is not guaranteed. ++ */ ++ cxlr = cxled->cxld.region; ++ if (cxlr) ++ dev_dbg(dev, "dpa:0x%llx mapped in region:%s\n", dpa, ++ dev_name(&cxlr->dev)); ++ else ++ dev_dbg(dev, "dpa:0x%llx mapped in endpoint:%s\n", dpa, ++ dev_name(dev)); + +- ctx->cxlr = cxled->cxld.region; ++ ctx->cxlr = cxlr; + + return 1; + } +-- +2.43.0 + diff --git a/queue-6.6/cxl-region-check-interleave-capability.patch b/queue-6.6/cxl-region-check-interleave-capability.patch new file mode 100644 index 00000000000..f714cd60eb5 --- /dev/null +++ b/queue-6.6/cxl-region-check-interleave-capability.patch @@ -0,0 +1,265 @@ +From 7caea46981f5e6c19054cbb510717555e6714451 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 14 Jun 2024 04:47:54 -0400 +Subject: cxl/region: check interleave capability + +From: Yao Xingtao + +[ Upstream commit 84328c5acebc10c8cdcf17283ab6c6d548885bfc ] + +Since interleave capability is not verified, if the interleave +capability of a target does not match the region need, committing decoder +should have failed at the device end. + +In order to checkout this error as quickly as possible, driver needs +to check the interleave capability of target during attaching it to +region. + +Per CXL specification r3.1(8.2.4.20.1 CXL HDM Decoder Capability Register), +bits 11 and 12 indicate the capability to establish interleaving in 3, 6, +12 and 16 ways. If these bits are not set, the target cannot be attached to +a region utilizing such interleave ways. + +Additionally, bits 8 and 9 represent the capability of the bits used for +interleaving in the address, Linux tracks this in the cxl_port +interleave_mask. + +Per CXL specification r3.1(8.2.4.20.13 Decoder Protection): + eIW means encoded Interleave Ways. + eIG means encoded Interleave Granularity. + + in HPA: + if eIW is 0 or 8 (interleave ways: 1, 3), all the bits of HPA are used, + the interleave bits are none, the following check is ignored. + + if eIW is less than 8 (interleave ways: 2, 4, 8, 16), the interleave bits + start at bit position eIG + 8 and end at eIG + eIW + 8 - 1. + + if eIW is greater than 8 (interleave ways: 6, 12), the interleave bits + start at bit position eIG + 8 and end at eIG + eIW - 1. + + if the interleave mask is insufficient to cover the required interleave + bits, the target cannot be attached to the region. + +Fixes: 384e624bb211 ("cxl/region: Attach endpoint decoders") +Signed-off-by: Yao Xingtao +Reviewed-by: Dan Williams +Reviewed-by: Jonathan Cameron +Link: https://patch.msgid.link/20240614084755.59503-2-yaoxt.fnst@fujitsu.com +Signed-off-by: Dave Jiang +Signed-off-by: Sasha Levin +--- + drivers/cxl/core/hdm.c | 13 ++++++ + drivers/cxl/core/region.c | 82 ++++++++++++++++++++++++++++++++++++ + drivers/cxl/cxl.h | 2 + + drivers/cxl/cxlmem.h | 10 +++++ + tools/testing/cxl/test/cxl.c | 4 ++ + 5 files changed, 111 insertions(+) + +diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c +index 90664659d5fab..3600b7cbfb589 100644 +--- a/drivers/cxl/core/hdm.c ++++ b/drivers/cxl/core/hdm.c +@@ -52,6 +52,14 @@ int devm_cxl_add_passthrough_decoder(struct cxl_port *port) + struct cxl_dport *dport = NULL; + int single_port_map[1]; + unsigned long index; ++ struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev); ++ ++ /* ++ * Capability checks are moot for passthrough decoders, support ++ * any and all possibilities. ++ */ ++ cxlhdm->interleave_mask = ~0U; ++ cxlhdm->iw_cap_mask = ~0UL; + + cxlsd = cxl_switch_decoder_alloc(port, 1); + if (IS_ERR(cxlsd)) +@@ -79,6 +87,11 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm) + cxlhdm->interleave_mask |= GENMASK(11, 8); + if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_14_12, hdm_cap)) + cxlhdm->interleave_mask |= GENMASK(14, 12); ++ cxlhdm->iw_cap_mask = BIT(1) | BIT(2) | BIT(4) | BIT(8); ++ if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY, hdm_cap)) ++ cxlhdm->iw_cap_mask |= BIT(3) | BIT(6) | BIT(12); ++ if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_16_WAY, hdm_cap)) ++ cxlhdm->iw_cap_mask |= BIT(16); + } + + static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb, +diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c +index 0d59af19ecee7..bc5a43897d578 100644 +--- a/drivers/cxl/core/region.c ++++ b/drivers/cxl/core/region.c +@@ -997,6 +997,26 @@ static int cxl_port_attach_region(struct cxl_port *port, + } + cxld = cxl_rr->decoder; + ++ /* ++ * the number of targets should not exceed the target_count ++ * of the decoder ++ */ ++ if (is_switch_decoder(&cxld->dev)) { ++ struct cxl_switch_decoder *cxlsd; ++ ++ cxlsd = to_cxl_switch_decoder(&cxld->dev); ++ if (cxl_rr->nr_targets > cxlsd->nr_targets) { ++ dev_dbg(&cxlr->dev, ++ "%s:%s %s add: %s:%s @ %d overflows targets: %d\n", ++ dev_name(port->uport_dev), dev_name(&port->dev), ++ dev_name(&cxld->dev), dev_name(&cxlmd->dev), ++ dev_name(&cxled->cxld.dev), pos, ++ cxlsd->nr_targets); ++ rc = -ENXIO; ++ goto out_erase; ++ } ++ } ++ + rc = cxl_rr_ep_add(cxl_rr, cxled); + if (rc) { + dev_dbg(&cxlr->dev, +@@ -1106,6 +1126,50 @@ static int check_last_peer(struct cxl_endpoint_decoder *cxled, + return 0; + } + ++static int check_interleave_cap(struct cxl_decoder *cxld, int iw, int ig) ++{ ++ struct cxl_port *port = to_cxl_port(cxld->dev.parent); ++ struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev); ++ unsigned int interleave_mask; ++ u8 eiw; ++ u16 eig; ++ int high_pos, low_pos; ++ ++ if (!test_bit(iw, &cxlhdm->iw_cap_mask)) ++ return -ENXIO; ++ /* ++ * Per CXL specification r3.1(8.2.4.20.13 Decoder Protection), ++ * if eiw < 8: ++ * DPAOFFSET[51: eig + 8] = HPAOFFSET[51: eig + 8 + eiw] ++ * DPAOFFSET[eig + 7: 0] = HPAOFFSET[eig + 7: 0] ++ * ++ * when the eiw is 0, all the bits of HPAOFFSET[51: 0] are used, the ++ * interleave bits are none. ++ * ++ * if eiw >= 8: ++ * DPAOFFSET[51: eig + 8] = HPAOFFSET[51: eig + eiw] / 3 ++ * DPAOFFSET[eig + 7: 0] = HPAOFFSET[eig + 7: 0] ++ * ++ * when the eiw is 8, all the bits of HPAOFFSET[51: 0] are used, the ++ * interleave bits are none. ++ */ ++ ways_to_eiw(iw, &eiw); ++ if (eiw == 0 || eiw == 8) ++ return 0; ++ ++ granularity_to_eig(ig, &eig); ++ if (eiw > 8) ++ high_pos = eiw + eig - 1; ++ else ++ high_pos = eiw + eig + 7; ++ low_pos = eig + 8; ++ interleave_mask = GENMASK(high_pos, low_pos); ++ if (interleave_mask & ~cxlhdm->interleave_mask) ++ return -ENXIO; ++ ++ return 0; ++} ++ + static int cxl_port_setup_targets(struct cxl_port *port, + struct cxl_region *cxlr, + struct cxl_endpoint_decoder *cxled) +@@ -1256,6 +1320,15 @@ static int cxl_port_setup_targets(struct cxl_port *port, + return -ENXIO; + } + } else { ++ rc = check_interleave_cap(cxld, iw, ig); ++ if (rc) { ++ dev_dbg(&cxlr->dev, ++ "%s:%s iw: %d ig: %d is not supported\n", ++ dev_name(port->uport_dev), ++ dev_name(&port->dev), iw, ig); ++ return rc; ++ } ++ + cxld->interleave_ways = iw; + cxld->interleave_granularity = ig; + cxld->hpa_range = (struct range) { +@@ -1692,6 +1765,15 @@ static int cxl_region_attach(struct cxl_region *cxlr, + struct cxl_dport *dport; + int rc = -ENXIO; + ++ rc = check_interleave_cap(&cxled->cxld, p->interleave_ways, ++ p->interleave_granularity); ++ if (rc) { ++ dev_dbg(&cxlr->dev, "%s iw: %d ig: %d is not supported\n", ++ dev_name(&cxled->cxld.dev), p->interleave_ways, ++ p->interleave_granularity); ++ return rc; ++ } ++ + if (cxled->mode != cxlr->mode) { + dev_dbg(&cxlr->dev, "%s region mode: %d mismatch: %d\n", + dev_name(&cxled->cxld.dev), cxlr->mode, cxled->mode); +diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h +index de2c250c894b1..bb3ad219b6b31 100644 +--- a/drivers/cxl/cxl.h ++++ b/drivers/cxl/cxl.h +@@ -43,6 +43,8 @@ + #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) + #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) + #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) ++#define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11) ++#define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12) + #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 + #define CXL_HDM_DECODER_ENABLE BIT(1) + #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) +diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h +index 6933bc20e76b6..59c7f88b915a4 100644 +--- a/drivers/cxl/cxlmem.h ++++ b/drivers/cxl/cxlmem.h +@@ -888,11 +888,21 @@ static inline void cxl_mem_active_dec(void) + + int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd); + ++/** ++ * struct cxl_hdm - HDM Decoder registers and cached / decoded capabilities ++ * @regs: mapped registers, see devm_cxl_setup_hdm() ++ * @decoder_count: number of decoders for this port ++ * @target_count: for switch decoders, max downstream port targets ++ * @interleave_mask: interleave granularity capability, see check_interleave_cap() ++ * @iw_cap_mask: bitmask of supported interleave ways, see check_interleave_cap() ++ * @port: mapped cxl_port, see devm_cxl_setup_hdm() ++ */ + struct cxl_hdm { + struct cxl_component_regs regs; + unsigned int decoder_count; + unsigned int target_count; + unsigned int interleave_mask; ++ unsigned long iw_cap_mask; + struct cxl_port *port; + }; + +diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c +index f4e517a0c7740..8251718eaf3a8 100644 +--- a/tools/testing/cxl/test/cxl.c ++++ b/tools/testing/cxl/test/cxl.c +@@ -624,11 +624,15 @@ static struct cxl_hdm *mock_cxl_setup_hdm(struct cxl_port *port, + struct cxl_endpoint_dvsec_info *info) + { + struct cxl_hdm *cxlhdm = devm_kzalloc(&port->dev, sizeof(*cxlhdm), GFP_KERNEL); ++ struct device *dev = &port->dev; + + if (!cxlhdm) + return ERR_PTR(-ENOMEM); + + cxlhdm->port = port; ++ cxlhdm->interleave_mask = ~0U; ++ cxlhdm->iw_cap_mask = ~0UL; ++ dev_set_drvdata(dev, cxlhdm); + return cxlhdm; + } + +-- +2.43.0 + diff --git a/queue-6.6/cxl-region-move-cxl_dpa_to_region-work-to-the-region.patch b/queue-6.6/cxl-region-move-cxl_dpa_to_region-work-to-the-region.patch new file mode 100644 index 00000000000..77ef86215ba --- /dev/null +++ b/queue-6.6/cxl-region-move-cxl_dpa_to_region-work-to-the-region.patch @@ -0,0 +1,158 @@ +From 9df921007bea4758217bdbf8f2b46cbd898df294 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Apr 2024 10:28:04 -0700 +Subject: cxl/region: Move cxl_dpa_to_region() work to the region driver + +From: Alison Schofield + +[ Upstream commit b98d042698a32518c93e47730e9ad86b387a9c21 ] + +This helper belongs in the region driver as it is only useful +with CONFIG_CXL_REGION. Add a stub in core.h for when the region +driver is not built. + +Signed-off-by: Alison Schofield +Reviewed-by: Jonathan Cameron +Reviewed-by: Ira Weiny +Link: https://lore.kernel.org/r/05e30f788d62b3dd398aff2d2ea50a6aaa7c3313.1714496730.git.alison.schofield@intel.com +Signed-off-by: Dave Jiang +Stable-dep-of: 285f2a088414 ("cxl/region: Avoid null pointer dereference in region lookup") +Signed-off-by: Sasha Levin +--- + drivers/cxl/core/core.h | 7 +++++++ + drivers/cxl/core/memdev.c | 44 --------------------------------------- + drivers/cxl/core/region.c | 44 +++++++++++++++++++++++++++++++++++++++ + 3 files changed, 51 insertions(+), 44 deletions(-) + +diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h +index 8e5f3d84311e5..6444cc827c9ce 100644 +--- a/drivers/cxl/core/core.h ++++ b/drivers/cxl/core/core.h +@@ -27,7 +27,14 @@ void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled); + int cxl_region_init(void); + void cxl_region_exit(void); + int cxl_get_poison_by_endpoint(struct cxl_port *port); ++struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa); ++ + #else ++static inline ++struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa) ++{ ++ return NULL; ++} + static inline int cxl_get_poison_by_endpoint(struct cxl_port *port) + { + return 0; +diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c +index 2f43d368ba073..eb895c70043fd 100644 +--- a/drivers/cxl/core/memdev.c ++++ b/drivers/cxl/core/memdev.c +@@ -251,50 +251,6 @@ int cxl_trigger_poison_list(struct cxl_memdev *cxlmd) + } + EXPORT_SYMBOL_NS_GPL(cxl_trigger_poison_list, CXL); + +-struct cxl_dpa_to_region_context { +- struct cxl_region *cxlr; +- u64 dpa; +-}; +- +-static int __cxl_dpa_to_region(struct device *dev, void *arg) +-{ +- struct cxl_dpa_to_region_context *ctx = arg; +- struct cxl_endpoint_decoder *cxled; +- u64 dpa = ctx->dpa; +- +- if (!is_endpoint_decoder(dev)) +- return 0; +- +- cxled = to_cxl_endpoint_decoder(dev); +- if (!cxled->dpa_res || !resource_size(cxled->dpa_res)) +- return 0; +- +- if (dpa > cxled->dpa_res->end || dpa < cxled->dpa_res->start) +- return 0; +- +- dev_dbg(dev, "dpa:0x%llx mapped in region:%s\n", dpa, +- dev_name(&cxled->cxld.region->dev)); +- +- ctx->cxlr = cxled->cxld.region; +- +- return 1; +-} +- +-static struct cxl_region *cxl_dpa_to_region(struct cxl_memdev *cxlmd, u64 dpa) +-{ +- struct cxl_dpa_to_region_context ctx; +- struct cxl_port *port; +- +- ctx = (struct cxl_dpa_to_region_context) { +- .dpa = dpa, +- }; +- port = cxlmd->endpoint; +- if (port && is_cxl_endpoint(port) && cxl_num_decoders_committed(port)) +- device_for_each_child(&port->dev, &ctx, __cxl_dpa_to_region); +- +- return ctx.cxlr; +-} +- + static int cxl_validate_poison_dpa(struct cxl_memdev *cxlmd, u64 dpa) + { + struct cxl_dev_state *cxlds = cxlmd->cxlds; +diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c +index 7a646fed17211..d2ce309434654 100644 +--- a/drivers/cxl/core/region.c ++++ b/drivers/cxl/core/region.c +@@ -2509,6 +2509,50 @@ int cxl_get_poison_by_endpoint(struct cxl_port *port) + return rc; + } + ++struct cxl_dpa_to_region_context { ++ struct cxl_region *cxlr; ++ u64 dpa; ++}; ++ ++static int __cxl_dpa_to_region(struct device *dev, void *arg) ++{ ++ struct cxl_dpa_to_region_context *ctx = arg; ++ struct cxl_endpoint_decoder *cxled; ++ u64 dpa = ctx->dpa; ++ ++ if (!is_endpoint_decoder(dev)) ++ return 0; ++ ++ cxled = to_cxl_endpoint_decoder(dev); ++ if (!cxled->dpa_res || !resource_size(cxled->dpa_res)) ++ return 0; ++ ++ if (dpa > cxled->dpa_res->end || dpa < cxled->dpa_res->start) ++ return 0; ++ ++ dev_dbg(dev, "dpa:0x%llx mapped in region:%s\n", dpa, ++ dev_name(&cxled->cxld.region->dev)); ++ ++ ctx->cxlr = cxled->cxld.region; ++ ++ return 1; ++} ++ ++struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa) ++{ ++ struct cxl_dpa_to_region_context ctx; ++ struct cxl_port *port; ++ ++ ctx = (struct cxl_dpa_to_region_context) { ++ .dpa = dpa, ++ }; ++ port = cxlmd->endpoint; ++ if (port && is_cxl_endpoint(port) && cxl_num_decoders_committed(port)) ++ device_for_each_child(&port->dev, &ctx, __cxl_dpa_to_region); ++ ++ return ctx.cxlr; ++} ++ + static struct lock_class_key cxl_pmem_region_key; + + static struct cxl_pmem_region *cxl_pmem_region_alloc(struct cxl_region *cxlr) +-- +2.43.0 + diff --git a/queue-6.6/series b/queue-6.6/series index 2ddd7642190..0926022e1ec 100644 --- a/queue-6.6/series +++ b/queue-6.6/series @@ -151,3 +151,13 @@ erofs-fix-null-dereference-of-dif-bdev_handle-in-fscache-mode.patch pwm-stm32-refuse-too-small-period-requests.patch revert-cpufreq-amd-pstate-fix-the-inconsistency-in-max-frequency-units.patch mm-page_alloc-separate-thp-pcp-into-movable-and-non-movable-categories.patch +arm64-dts-rockchip-fix-sd-nand-and-emmc-init-on-rk33.patch +arm64-dts-rockchip-rename-led-related-pinctrl-nodes-.patch +arm64-dts-rockchip-fix-the-value-of-dlg-jack-det-rat.patch +arm-dts-rockchip-rk3066a-add-sound-dai-cells-to-hdmi.patch +arm64-dts-rockchip-make-poweroff-8-work-on-radxa-roc.patch +arm64-dts-rockchip-fix-pmic-interrupt-pin-on-rock-pi.patch +arm64-dts-rockchip-add-sound-dai-cells-for-rk3368.patch +cxl-region-move-cxl_dpa_to_region-work-to-the-region.patch +cxl-region-avoid-null-pointer-dereference-in-region-.patch +cxl-region-check-interleave-capability.patch