From: Alexandru Gagniuc Date: Wed, 14 May 2025 02:31:48 +0000 (-0500) Subject: qualcommbe: v6.12: add pending patches X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=01f362496090ae87a25aaedfc2a57458affd6bae;p=thirdparty%2Fopenwrt.git qualcommbe: v6.12: add pending patches Add dts fixes from linux-next. Two patches from the NSSCC series are still in -next did not yet land in mainline, as well as misc other DTS changes. Add them here. Signed-off-by: Alexandru Gagniuc Link: https://github.com/openwrt/openwrt/pull/18796 Signed-off-by: Robert Marko --- diff --git a/target/linux/qualcommbe/patches-6.12/0100-arm64-dts-qcom-ipq9574-Add-nsscc-node.patch b/target/linux/qualcommbe/patches-6.12/0100-arm64-dts-qcom-ipq9574-Add-nsscc-node.patch new file mode 100644 index 00000000000..b746ed8d543 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0100-arm64-dts-qcom-ipq9574-Add-nsscc-node.patch @@ -0,0 +1,54 @@ +From 52ebd52aa1906961142a2aba55d47a53b956847c Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 13 Mar 2025 16:33:58 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq9574: Add nsscc node + +Add a node for the nss clock controller found on ipq9574 based devices. + +Reviewed-by: Konrad Dybcio +Signed-off-by: Devi Priya +Signed-off-by: Manikanta Mylavarapu +Link: https://lore.kernel.org/r/20250313110359.242491-6-quic_mmanikan@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 29 +++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -1193,6 +1193,35 @@ + status = "disabled"; + }; + ++ nsscc: clock-controller@39b00000 { ++ compatible = "qcom,ipq9574-nsscc"; ++ reg = <0x39b00000 0x80000>; ++ clocks = <&xo_board_clk>, ++ <&cmn_pll NSS_1200MHZ_CLK>, ++ <&cmn_pll PPE_353MHZ_CLK>, ++ <&gcc GPLL0_OUT_AUX>, ++ <0>, ++ <0>, ++ <0>, ++ <0>, ++ <0>, ++ <0>, ++ <&gcc GCC_NSSCC_CLK>; ++ clock-names = "xo", ++ "nss_1200", ++ "ppe_353", ++ "gpll0_out", ++ "uniphy0_rx", ++ "uniphy0_tx", ++ "uniphy1_rx", ++ "uniphy1_tx", ++ "uniphy2_rx", ++ "uniphy2_tx", ++ "bus"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ #interconnect-cells = <1>; ++ }; + }; + + thermal-zones { diff --git a/target/linux/qualcommbe/patches-6.12/0101-arm64-dts-qcom-ipq9574-fix-the-msi-interrupt-numbers.patch b/target/linux/qualcommbe/patches-6.12/0101-arm64-dts-qcom-ipq9574-fix-the-msi-interrupt-numbers.patch new file mode 100644 index 00000000000..774e88a8aa0 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0101-arm64-dts-qcom-ipq9574-fix-the-msi-interrupt-numbers.patch @@ -0,0 +1,44 @@ +From 2f2f5ae4d52ea882ba58f6b2fa6373a3d3db2bce Mon Sep 17 00:00:00 2001 +From: Manikanta Mylavarapu +Date: Thu, 13 Mar 2025 12:44:22 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq9574: fix the msi interrupt numbers of + pcie3 + +The MSI interrupt numbers of the PCIe3 controller are incorrect. Due +to this, the functional bring up of the QDSP6 processor on the PCIe +endpoint has failed. Correct the MSI interrupt numbers to properly +bring up the QDSP6 processor on the PCIe endpoint. + +Fixes: d80c7fbfa908 ("arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes") +Signed-off-by: Manikanta Mylavarapu +Link: https://lore.kernel.org/r/20250313071422.510-1-quic_mmanikan@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -972,14 +972,14 @@ + ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>, + <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>; + +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; + interrupt-names = "msi0", + "msi1", + "msi2", diff --git a/target/linux/qualcommbe/patches-6.12/0102-arm64-dts-qcom-ipq9574-Fix-USB-vdd-info.patch b/target/linux/qualcommbe/patches-6.12/0102-arm64-dts-qcom-ipq9574-Fix-USB-vdd-info.patch new file mode 100644 index 00000000000..dbf75c26d60 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0102-arm64-dts-qcom-ipq9574-Fix-USB-vdd-info.patch @@ -0,0 +1,55 @@ +From 3857f7cf650fa4ae0047b9b6fea6f7cd242de29c Mon Sep 17 00:00:00 2001 +From: Varadarajan Narayanan +Date: Fri, 7 Feb 2025 13:05:45 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq9574: Fix USB vdd info + +USB phys in ipq9574 use the 'L5' regulator. The commit ec4f047679d5 +("arm64: dts: qcom: ipq9574: Enable USB") incorrectly specified it as +'L2'. Because of this when the phy module turns off/on its regulators, +the wrong regulator is turned off/on resulting in 2 issues, namely the +correct regulator related to the USB phy is not turned off/on and the +module powered by the incorrect regulator is affected. + +Fixes: ec4f047679d5 ("arm64: dts: qcom: ipq9574: Enable USB") +Signed-off-by: Varadarajan Narayanan +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20250207073545.1768990-2-quic_varada@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +@@ -111,6 +111,13 @@ + regulator-always-on; + regulator-boot-on; + }; ++ ++ mp5496_l5: l5 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; + }; + }; + +@@ -146,7 +153,7 @@ + }; + + &usb_0_qmpphy { +- vdda-pll-supply = <&mp5496_l2>; ++ vdda-pll-supply = <&mp5496_l5>; + vdda-phy-supply = <®ulator_fixed_0p925>; + + status = "okay"; +@@ -154,7 +161,7 @@ + + &usb_0_qusbphy { + vdd-supply = <®ulator_fixed_0p925>; +- vdda-pll-supply = <&mp5496_l2>; ++ vdda-pll-supply = <&mp5496_l5>; + vdda-phy-dpdm-supply = <®ulator_fixed_3p3>; + + status = "okay"; diff --git a/target/linux/qualcommbe/patches-6.12/0103-arm64-dts-qcom-ipq9574-Add-SPI-nand-support.patch b/target/linux/qualcommbe/patches-6.12/0103-arm64-dts-qcom-ipq9574-Add-SPI-nand-support.patch new file mode 100644 index 00000000000..f37c08b250e --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0103-arm64-dts-qcom-ipq9574-Add-SPI-nand-support.patch @@ -0,0 +1,50 @@ +From 583299efa34c4a484b211f84c63aee78b6c2b469 Mon Sep 17 00:00:00 2001 +From: Md Sadre Alam +Date: Thu, 6 Mar 2025 17:03:55 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq9574: Add SPI nand support + +Add SPI NAND support for ipq9574 SoC. + +Signed-off-by: Md Sadre Alam +Link: https://lore.kernel.org/r/20250306113357.126602-2-quic_mdalam@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 +++++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -673,6 +673,33 @@ + status = "disabled"; + }; + ++ qpic_bam: dma-controller@7984000 { ++ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; ++ reg = <0x07984000 0x1c000>; ++ interrupts = ; ++ clocks = <&gcc GCC_QPIC_AHB_CLK>; ++ clock-names = "bam_clk"; ++ #dma-cells = <1>; ++ qcom,ee = <0>; ++ status = "disabled"; ++ }; ++ ++ qpic_nand: spi@79b0000 { ++ compatible = "qcom,ipq9574-snand"; ++ reg = <0x079b0000 0x10000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&gcc GCC_QPIC_CLK>, ++ <&gcc GCC_QPIC_AHB_CLK>, ++ <&gcc GCC_QPIC_IO_MACRO_CLK>; ++ clock-names = "core", "aon", "iom"; ++ dmas = <&qpic_bam 0>, ++ <&qpic_bam 1>, ++ <&qpic_bam 2>; ++ dma-names = "tx", "rx", "cmd"; ++ status = "disabled"; ++ }; ++ + usb_0_qusbphy: phy@7b000 { + compatible = "qcom,ipq9574-qusb2-phy"; + reg = <0x0007b000 0x180>; diff --git a/target/linux/qualcommbe/patches-6.12/0104-arm64-dts-qcom-ipq9574-Enable-SPI-NAND-for-ipq9574.patch b/target/linux/qualcommbe/patches-6.12/0104-arm64-dts-qcom-ipq9574-Enable-SPI-NAND-for-ipq9574.patch new file mode 100644 index 00000000000..393923a343a --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0104-arm64-dts-qcom-ipq9574-Enable-SPI-NAND-for-ipq9574.patch @@ -0,0 +1,68 @@ +From a7c88bc81632974c0708308493aefb1f871b65fa Mon Sep 17 00:00:00 2001 +From: Md Sadre Alam +Date: Thu, 6 Mar 2025 17:03:56 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq9574: Enable SPI NAND for ipq9574 + +Enable SPI NAND support for ipq9574 SoC. + +Reviewed-by: Konrad Dybcio +Signed-off-by: Md Sadre Alam +Link: https://lore.kernel.org/r/20250306113357.126602-3-quic_mdalam@quicinc.com +Signed-off-by: Bjorn Andersson +--- + .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 44 +++++++++++++++++++ + 1 file changed, 44 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +@@ -146,6 +146,50 @@ + drive-strength = <8>; + bias-pull-up; + }; ++ ++ qpic_snand_default_state: qpic-snand-default-state { ++ clock-pins { ++ pins = "gpio5"; ++ function = "qspi_clk"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ ++ cs-pins { ++ pins = "gpio4"; ++ function = "qspi_cs"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ ++ data-pins { ++ pins = "gpio0", "gpio1", "gpio2", "gpio3"; ++ function = "qspi_data"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; ++}; ++ ++&qpic_bam { ++ status = "okay"; ++}; ++ ++&qpic_nand { ++ pinctrl-0 = <&qpic_snand_default_state>; ++ pinctrl-names = "default"; ++ ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ nand-ecc-engine = <&qpic_nand>; ++ nand-ecc-strength = <4>; ++ nand-ecc-step-size = <512>; ++ }; + }; + + &usb_0_dwc3 { diff --git a/target/linux/qualcommbe/patches-6.12/0105-arm64-dts-qcom-ipq9574-Remove-eMMC-node.patch b/target/linux/qualcommbe/patches-6.12/0105-arm64-dts-qcom-ipq9574-Remove-eMMC-node.patch new file mode 100644 index 00000000000..d188539aaa7 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0105-arm64-dts-qcom-ipq9574-Remove-eMMC-node.patch @@ -0,0 +1,37 @@ +From 0156e327aa854be5eb9cbec9d020be1026b5b446 Mon Sep 17 00:00:00 2001 +From: Md Sadre Alam +Date: Thu, 6 Mar 2025 17:03:57 +0530 +Subject: [PATCH] arm64: dts: qcom: ipq9574: Remove eMMC node + +Remove eMMC node for rdp433, since rdp433 +default boot mode is norplusnand + +Reviewed-by: Konrad Dybcio +Signed-off-by: Md Sadre Alam +Link: https://lore.kernel.org/r/20250306113357.126602-4-quic_mdalam@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 12 ------------ + 1 file changed, 12 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +@@ -55,18 +55,6 @@ + status = "okay"; + }; + +-&sdhc_1 { +- pinctrl-0 = <&sdc_default_state>; +- pinctrl-names = "default"; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- max-frequency = <384000000>; +- bus-width = <8>; +- status = "okay"; +-}; +- + &tlmm { + + pcie1_default: pcie1-default-state {