From: Jeff Law Date: Fri, 1 May 2026 12:47:07 +0000 (-0600) Subject: [PR target/124559][RISC-V] Improve RISC-V constant synthesis for some HImode constants X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=022afdcb9b71f776b825e3d7d148cd73e33b720f;p=thirdparty%2Fgcc.git [PR target/124559][RISC-V] Improve RISC-V constant synthesis for some HImode constants So this is a trivial little bug we found doing some comparisons against LLVM. For the function sub2 in load-immediate.c we get this code: li a5,-32768 sh a5,0(a0) xori a5,a5,-1 sh a5,0(a1) Note carefully that li+xori. There's a slightly better sequence here from an encoding standpoint. Instead of using xori we can adjust the synthesis sequence to target an "addi" for that statement and in doing so we can save two code bytes of space. The xori sequence was used because we can't do this in gcc: (set (dest:HI) (const_int 0x8000)) We're in HI mode so the constant must be sign extended from bit 15 to a HOST_WIDE_INT. Fixing this isn't hard. The key is realizing the vast majority of the time we really don't want/need to load in HImode and in fact we're typically going to be generating objects in word_mode. So instead of passing in the pre-promoted mode, pass in the post-promoted mode. That's fine and good with one caveat. CSE fails to use NEG/NOT to derive a new constant from an older constant, even if the cost is smaller, which caused a code quality regression elsewhere on the RISC-V port. So this patch adjusts CSE ever-so-slightly to allow it to derive constants from a previous constant using NOT/NEG in a fairly obvious way. This has been in my tester for a while, so it's been through the usual bootstrap & regression test on the Pioneer, BPI, x86 and aarch64 and others as well as testing across the various embedded targets. Waiting on pre-commit testing to do its thing. PR target/124559 gcc/ * config/riscv/riscv-protos.h (riscv_move_integer): Drop mode argument. * config/riscv/riscv.cc (riscv_move_integer): Pass mode after promotions to riscv_build_integer. All callers changed. * config/riscv/riscv.md: Corresponding changes. * cse.cc (cse_insn): Try to derive one constant from another using NOT/NEG. --- diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index dd029c70413..494feb4458d 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -119,7 +119,7 @@ extern rtx riscv_emit_move (rtx, rtx); extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *); extern bool riscv_split_symbol_type (enum riscv_symbol_type); extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type); -extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode); +extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT); extern bool riscv_legitimize_move (machine_mode, rtx, rtx); extern rtx riscv_subword (rtx, bool); extern bool riscv_split_64bit_move_p (rtx, rtx); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 97272b4349a..b936e3c272f 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1736,15 +1736,15 @@ riscv_split_integer (HOST_WIDE_INT val, machine_mode mode) bool eq_neg = (loval == hival) && ((loval & 0x80000000) != 0); if (eq_neg) - riscv_move_integer (lo, lo, ~loval & 0xffffffff, mode); + riscv_move_integer (lo, lo, ~loval & 0xffffffff); else - riscv_move_integer (lo, lo, loval, mode); + riscv_move_integer (lo, lo, loval); if (loval == hival) hi = gen_rtx_ASHIFT (mode, lo, GEN_INT (32)); else { - riscv_move_integer (hi, hi, hival, mode); + riscv_move_integer (hi, hi, hival); hi = gen_rtx_ASHIFT (mode, hi, GEN_INT (32)); } @@ -3275,8 +3275,7 @@ riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, is the original src mode before promotion. */ void -riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value, - machine_mode orig_mode) +riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value) { struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS]; machine_mode mode; @@ -3284,9 +3283,10 @@ riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value, rtx x = NULL_RTX; mode = GET_MODE (dest); - /* We use the original mode for the riscv_build_integer call, because HImode - values are given special treatment. */ - num_ops = riscv_build_integer (codes, value, orig_mode, can_create_pseudo_p ()); + /* This originally passed in a mode prior to promotions, but what we really + need to do is pass in the mode of the destination, that's what ultimately + determines how a constant needs to be canonicalized. */ + num_ops = riscv_build_integer (codes, value, mode, can_create_pseudo_p ()); if (can_create_pseudo_p () && num_ops > 2 /* not a simple constant */ && num_ops >= riscv_split_integer_cost (value)) @@ -3383,7 +3383,7 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) /* Split moves of big integers into smaller pieces. */ if (splittable_const_int_operand (src, mode)) { - riscv_move_integer (dest, dest, INTVAL (src), mode); + riscv_move_integer (dest, dest, INTVAL (src)); return; } @@ -3970,7 +3970,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) if (splittable_const_int_operand (src, mode)) { reg = gen_reg_rtx (promoted_mode); - riscv_move_integer (reg, reg, INTVAL (src), mode); + riscv_move_integer (reg, reg, INTVAL (src)); } else reg = force_reg (promoted_mode, src); diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 6b5f824109e..ee44132291f 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2504,8 +2504,7 @@ "" [(const_int 0)] { - riscv_move_integer (operands[2], operands[0], INTVAL (operands[1]), - mode); + riscv_move_integer (operands[2], operands[0], INTVAL (operands[1])); DONE; }) @@ -2538,8 +2537,7 @@ "&& 1" [(const_int 0)] { - riscv_move_integer (operands[0], operands[0], INTVAL (operands[1]), - mode); + riscv_move_integer (operands[0], operands[0], INTVAL (operands[1])); DONE; } [(set_attr "type" "move")]) diff --git a/gcc/cse.cc b/gcc/cse.cc index 25b2bf500a9..b4b39e3ebf8 100644 --- a/gcc/cse.cc +++ b/gcc/cse.cc @@ -4980,6 +4980,34 @@ cse_insn (rtx_insn *insn) } } + /* If SRC_EQV is a CONST_INT, try looking up some related + constants (logical and arithmetic negation). Those may + ultimately be cheaper to re-use. */ + if (GET_CODE (src) != CONST_INT + && GET_CODE (src) != REG + && GET_CODE (src) != SUBREG + && src_const + && GET_CODE (src_const) == CONST_INT) + { + rtx trial_rtx = GEN_INT (~UINTVAL (src_const)); + struct table_elt *tmp = lookup (trial_rtx, HASH (trial_rtx, mode), mode); + rtx_code code = NOT; + if (!tmp) + { + trial_rtx = GEN_INT (-UINTVAL (src_const)); + tmp = lookup (trial_rtx, HASH (trial_rtx, mode), mode); + code = NEG; + } + + if (tmp) + { + src_related = gen_rtx_fmt_e (code, mode, tmp->first_same_value->exp); + src_eqv_here = src_related; + src_related_is_const_anchor = true; + } + + } + /* See if a MEM has already been loaded with a widening operation; if it has, we can use a subreg of that. Many CISC machines also have such operations, but this is only likely to be