From: João Date: Mon, 20 Apr 2026 20:32:03 +0000 (-0300) Subject: ASoC: mchp-spdifrx: Replace manual bitfield manipulations with macros and typo correction X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0241d6192a11c8f8634ab10a3a26fbdec92a9b08;p=thirdparty%2Fkernel%2Flinux.git ASoC: mchp-spdifrx: Replace manual bitfield manipulations with macros and typo correction Replace manual bitfield manipulations with FIELD_GET() and FIELD_PREP() in order to improve code readability, security and manageability. Also correcting GENAMSK typo for GENMASK. Signed-off-by: João Marinho Co-developed-by: Micael Vinicius Signed-off-by: Micael Vinicius Link: https://patch.msgid.link/20260420203218.15060-1-joao.bcc@usp.br Signed-off-by: Mark Brown --- diff --git a/sound/soc/atmel/mchp-spdifrx.c b/sound/soc/atmel/mchp-spdifrx.c index 521bee4998f8d..2c47aabdca95d 100644 --- a/sound/soc/atmel/mchp-spdifrx.c +++ b/sound/soc/atmel/mchp-spdifrx.c @@ -6,6 +6,7 @@ // // Author: Codrin Ciubotariu +#include #include #include #include @@ -41,6 +42,13 @@ #define SPDIFRX_VERSION 0xFC /* Version Register */ + +/* 32-bit word byte masks */ +#define SPDIFRX_BYTE_0_MASK GENMASK(7, 0) +#define SPDIFRX_BYTE_1_MASK GENMASK(15, 8) +#define SPDIFRX_BYTE_2_MASK GENMASK(23, 16) +#define SPDIFRX_BYTE_3_MASK GENMASK(31, 24) + /* * ---- Control Register (Write-only) ---- */ @@ -55,7 +63,7 @@ #define SPDIFRX_MR_RXEN_ENABLE (1 << 0) /* SPDIF Receiver Enabled */ /* Validity Bit Mode */ -#define SPDIFRX_MR_VBMODE_MASK GENAMSK(1, 1) +#define SPDIFRX_MR_VBMODE_MASK GENMASK(1, 1) #define SPDIFRX_MR_VBMODE_ALWAYS_LOAD \ (0 << 1) /* Load sample regardless of validity bit value */ #define SPDIFRX_MR_VBMODE_DISCARD_IF_VB1 \ @@ -74,7 +82,7 @@ /* Sample Data Width */ #define SPDIFRX_MR_DATAWIDTH_MASK GENMASK(5, 4) #define SPDIFRX_MR_DATAWIDTH(width) \ - (((6 - (width) / 4) << 4) & SPDIFRX_MR_DATAWIDTH_MASK) + FIELD_PREP(SPDIFRX_MR_DATAWIDTH_MASK, 6 - ((width) / 4)) /* Packed Data Mode in Receive Holding Register */ #define SPDIFRX_MR_PACK_MASK GENMASK(7, 7) @@ -118,15 +126,14 @@ #define SPDIFRX_RSR_LOWF BIT(2) #define SPDIFRX_RSR_NOSIGNAL BIT(3) #define SPDIFRX_RSR_IFS_MASK GENMASK(27, 16) -#define SPDIFRX_RSR_IFS(reg) \ - (((reg) & SPDIFRX_RSR_IFS_MASK) >> 16) +#define SPDIFRX_RSR_IFS(reg) FIELD_GET(SPDIFRX_RSR_IFS_MASK, reg) /* * ---- Version Register (Read-only) ---- */ #define SPDIFRX_VERSION_MASK GENMASK(11, 0) #define SPDIFRX_VERSION_MFN_MASK GENMASK(18, 16) -#define SPDIFRX_VERSION_MFN(reg) (((reg) & SPDIFRX_VERSION_MFN_MASK) >> 16) +#define SPDIFRX_VERSION_MFN(reg) FIELD_GET(SPDIFRX_VERSION_MFN_MASK, reg) static bool mchp_spdifrx_readable_reg(struct device *dev, unsigned int reg) { @@ -317,10 +324,10 @@ static void mchp_spdifrx_channel_status_read(struct mchp_spdifrx_dev *dev, for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat[channel].data) / 4; i++) { regmap_read(dev->regmap, SPDIFRX_CHSR(channel, i), &val); - *ch_stat++ = val & 0xFF; - *ch_stat++ = (val >> 8) & 0xFF; - *ch_stat++ = (val >> 16) & 0xFF; - *ch_stat++ = (val >> 24) & 0xFF; + *ch_stat++ = FIELD_GET(SPDIFRX_BYTE_0_MASK, val); + *ch_stat++ = FIELD_GET(SPDIFRX_BYTE_1_MASK, val); + *ch_stat++ = FIELD_GET(SPDIFRX_BYTE_2_MASK, val); + *ch_stat++ = FIELD_GET(SPDIFRX_BYTE_3_MASK, val); } } @@ -334,10 +341,10 @@ static void mchp_spdifrx_channel_user_data_read(struct mchp_spdifrx_dev *dev, for (i = 0; i < ARRAY_SIZE(ctrl->user_data[channel].data) / 4; i++) { regmap_read(dev->regmap, SPDIFRX_CHUD(channel, i), &val); - *user_data++ = val & 0xFF; - *user_data++ = (val >> 8) & 0xFF; - *user_data++ = (val >> 16) & 0xFF; - *user_data++ = (val >> 24) & 0xFF; + *user_data++ = FIELD_GET(SPDIFRX_BYTE_0_MASK, val); + *user_data++ = FIELD_GET(SPDIFRX_BYTE_1_MASK, val); + *user_data++ = FIELD_GET(SPDIFRX_BYTE_2_MASK, val); + *user_data++ = FIELD_GET(SPDIFRX_BYTE_3_MASK, val); } }