From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Date: Mon, 13 Mar 2023 14:17:57 +0000 (+0800)
Subject: RISC-V: Use reg_or_subregno to check regno [PR109092]
X-Git-Tag: basepoints/gcc-14~474
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=02880e7803b19c357718abd2f0d567b4a761f318;p=thirdparty%2Fgcc.git

RISC-V: Use reg_or_subregno to check regno [PR109092]

gcc/ChangeLog:

	PR target/109092
	* config/riscv/riscv.md: Fix subreg bug.
---

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 863400cd447a..bc384d9aedf1 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1369,8 +1369,8 @@
 	(zero_extend:DI
 	    (match_operand:SI 1 "nonimmediate_operand" " r,m")))]
   "TARGET_64BIT && !TARGET_ZBA
-   && !(REG_P (operands[1])
-        && REGNO (operands[1]) == VL_REGNUM)"
+   && !(register_operand (operands[1], SImode)
+        && reg_or_subregno (operands[1]) == VL_REGNUM)"
   "@
    #
    lwu\t%0,%1"
@@ -1752,7 +1752,7 @@
   "(register_operand (operands[0], SImode)
     || reg_or_0_operand (operands[1], SImode))
     && !(register_operand (operands[1], SImode)
-         && REGNO (operands[1]) == VL_REGNUM)"
+         && reg_or_subregno (operands[1]) == VL_REGNUM)"
   { return riscv_output_move (operands[0], operands[1]); }
   [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore,rdvlenb")
    (set_attr "mode" "SI")