From: Grzegorz Jaszczyk Date: Thu, 25 Sep 2014 11:17:18 +0000 (+0200) Subject: irqchip: armada-370-xp: Fix MSI interrupt handling X-Git-Tag: v3.17.3~17 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=03090719a0da6ab35509c8037c06a2491bb64fa4;p=thirdparty%2Fkernel%2Fstable.git irqchip: armada-370-xp: Fix MSI interrupt handling commit 298dcb2dd0267d51e4f7c94a628cd0765a50ad75 upstream. The MSI interrupts use the 16 high doorbells, which are notified by using IRQ1 of the main interrupt controller. The MSI interrupts were handled correctly for Armada-XP and Armada-370 but not for Armada-375 and Armada-38x, which use chained handler for the MPIC. This commit fixes that by checking proper interrupt number in chained handler for the MPIC. Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Gregory CLEMENT Fixes: bc69b8adfe22 ("irqchip: armada-370-xp: Setup a chained handler for the MPIC") Acked-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1411643839-64925-2-git-send-email-jaz@semihalf.com Signed-off-by: Jason Cooper Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index 574aba0eba4e0..91424c481782a 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -417,9 +417,9 @@ static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq, irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE); - if (irqmap & BIT(0)) { + if (irqmap & BIT(1)) { armada_370_xp_handle_msi_irq(NULL, true); - irqmap &= ~BIT(0); + irqmap &= ~BIT(1); } for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {