From: Julian Seward <jseward@acm.org>
Date: Thu, 29 Jul 2010 05:13:58 +0000 (+0000)
Subject: Ignore a redundant REX.W prefix on an MMX pinsrw instruction
X-Git-Tag: svn/VALGRIND_3_6_1^2~81
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=03dc4052d3edcc56268c53ecc02dcb5957f802de;p=thirdparty%2Fvalgrind.git

Ignore a redundant REX.W prefix on an MMX pinsrw instruction
(Dan Gohman, dgohman@gmail.com).  Fixes #239992.


git-svn-id: svn://svn.valgrind.org/vex/trunk@1991
---

diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c
index 8fc2ff4029..21d5b6f2d6 100644
--- a/VEX/priv/guest_amd64_toIR.c
+++ b/VEX/priv/guest_amd64_toIR.c
@@ -9951,7 +9951,8 @@ DisResult disInstr_AMD64_WRK (
    /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
    /* 0F C4 = PINSRW -- get 16 bits from E(mem or low half ireg) and
       put it into the specified lane of mmx(G). */
-   if (haveNo66noF2noF3(pfx) && sz == 4 
+   if (haveNo66noF2noF3(pfx)
+       && (sz == 4 || /* ignore redundant REX.W */ sz == 8)
        && insn[0] == 0x0F && insn[1] == 0xC4) {
       /* Use t0 .. t3 to hold the 4 original 16-bit lanes of the
          mmx reg.  t4 is the new lane value.  t5 is the original