From: Hans Zhang <18255117159@163.com> Date: Fri, 13 Mar 2026 16:55:21 +0000 (+0800) Subject: PCI: controller: Validate max-link-speed X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=03f920936977b5133a0e57a7c9fdeb4e584eeb06;p=thirdparty%2Fkernel%2Fstable.git PCI: controller: Validate max-link-speed Add validation for the "max-link-speed" DT property in three more drivers, using the pcie_get_link_speed() helper. - brcmstb: If the value is missing or invalid, fall back to no limitation (pcie->gen = 0). Fix the previous incorrect logic. - mediatek-gen3: If the value is missing or invalid, use the maximum speed supported by the controller. - rzg3s-host: If the value is missing or invalid, fall back to Gen2. This ensures that all users of of_pci_get_max_link_speed() are ready for the removal of the central range check. Signed-off-by: Hans Zhang <18255117159@163.com> Signed-off-by: Manivannan Sadhasivam Reviewed-by: Florian Fainelli Link: https://patch.msgid.link/20260313165522.123518-5-18255117159@163.com --- diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 062f55690012..714bcab97b60 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1442,7 +1442,7 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta); nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta); dev_info(dev, "link up, %s x%u %s\n", - pci_speed_string(pcie_link_speed[cls]), nlw, + pci_speed_string(pcie_get_link_speed(cls)), nlw, ssc_good ? "(SSC)" : "(!SSC)"); return 0; @@ -2072,7 +2072,8 @@ static int brcm_pcie_probe(struct platform_device *pdev) return PTR_ERR(pcie->clk); ret = of_pci_get_max_link_speed(np); - pcie->gen = (ret < 0) ? 0 : ret; + if (pcie_get_link_speed(ret) == PCI_SPEED_UNKNOWN) + pcie->gen = 0; pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 75ddb8bee168..3b903ef7d3cf 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -1150,7 +1150,7 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) return err; err = of_pci_get_max_link_speed(pcie->dev->of_node); - if (err) { + if (pcie_get_link_speed(err) != PCI_SPEED_UNKNOWN) { /* Get the maximum speed supported by the controller */ max_speed = mtk_pcie_get_controller_max_link_speed(pcie); diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c index 2809112e6317..00a11f986117 100644 --- a/drivers/pci/controller/pcie-rzg3s-host.c +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -966,7 +966,7 @@ static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host) ls = readw_relaxed(host->pcie + pcie_cap + PCI_EXP_LNKSTA); cs2 = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2); - switch (pcie_link_speed[host->max_link_speed]) { + switch (pcie_get_link_speed(host->max_link_speed)) { case PCIE_SPEED_5_0GT: max_supported_link_speeds = GENMASK(PCI_EXP_LNKSTA_CLS_5_0GB - 1, 0); link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;