From: Maciej W. Rozycki <macro@embecosm.com>
Date: Wed, 22 Nov 2023 01:18:24 +0000 (+0000)
Subject: RISC-V: Fix `mode' usage in `riscv_expand_conditional_move'
X-Git-Tag: basepoints/gcc-15~4435
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=04c9c27c6f34a1ce1cd4900ccc8dc2521852e8e6;p=thirdparty%2Fgcc.git

RISC-V: Fix `mode' usage in `riscv_expand_conditional_move'

In `riscv_expand_conditional_move' `mode' is initialized right away from
`GET_MODE (dest)', so remove needless references that refrain from using
the local variable.

	gcc/
	* config/riscv/riscv.cc (riscv_expand_conditional_move): Use
	`mode' for `GET_MODE (dest)' throughout.
---

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 453c5f17196c..d37ffb307c72 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4028,8 +4028,8 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
 	 arm of the conditional move.  That allows us to support more
 	 cases for extensions which are more general than SFB.  But
 	 does mean we need to force CONS into a register at this point.  */
-      cons = force_reg (GET_MODE (dest), cons);
-      emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
+      cons = force_reg (mode, cons);
+      emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode,
 							  cond, cons, alt)));
       return true;
     }