From: Pat Haugen Date: Thu, 27 Aug 2015 18:42:04 +0000 (+0000) Subject: vector.md (vec_shr_): Fix to do a shift instead of a rotate. X-Git-Tag: releases/gcc-4.9.4~629 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=04d6cde001e6ec032483f3356b9435f664ca14dc;p=thirdparty%2Fgcc.git vector.md (vec_shr_): Fix to do a shift instead of a rotate. * config/rs6000/vector.md (vec_shr_): Fix to do a shift instead of a rotate. * gcc.target/powerpc/vec-shr.c: New. From-SVN: r227273 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8f7d21691152..04577f836856 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2015-08-27 Pat Haugen + + Backport from mainline: + 2015-08-27 Pat Haugen + + * config/rs6000/vector.md (vec_shr_): Fix to do a shift + instead of a rotate. + 2015-08-24 Michael Meissner Back port from mainline: diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index edbb83161d14..d81cccdf7289 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -988,6 +988,7 @@ rtx bitshift = operands[2]; rtx shift; rtx insn; + rtx zero_reg; HOST_WIDE_INT bitshift_val; HOST_WIDE_INT byteshift_val; @@ -997,16 +998,18 @@ if (bitshift_val & 0x7) FAIL; byteshift_val = bitshift_val >> 3; + zero_reg = gen_reg_rtx (mode); + emit_move_insn (zero_reg, CONST0_RTX (mode)); if (TARGET_VSX && (byteshift_val & 0x3) == 0) { shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2); - insn = gen_vsx_xxsldwi_ (operands[0], operands[1], operands[1], + insn = gen_vsx_xxsldwi_ (operands[0], operands[1], zero_reg, shift); } else { shift = gen_rtx_CONST_INT (QImode, byteshift_val); - insn = gen_altivec_vsldoi_ (operands[0], operands[1], operands[1], + insn = gen_altivec_vsldoi_ (operands[0], operands[1], zero_reg, shift); } @@ -1029,6 +1032,7 @@ rtx bitshift = operands[2]; rtx shift; rtx insn; + rtx zero_reg; HOST_WIDE_INT bitshift_val; HOST_WIDE_INT byteshift_val; @@ -1038,16 +1042,18 @@ if (bitshift_val & 0x7) FAIL; byteshift_val = 16 - (bitshift_val >> 3); + zero_reg = gen_reg_rtx (mode); + emit_move_insn (zero_reg, CONST0_RTX (mode)); if (TARGET_VSX && (byteshift_val & 0x3) == 0) { shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2); - insn = gen_vsx_xxsldwi_ (operands[0], operands[1], operands[1], + insn = gen_vsx_xxsldwi_ (operands[0], zero_reg, operands[1], shift); } else { shift = gen_rtx_CONST_INT (QImode, byteshift_val); - insn = gen_altivec_vsldoi_ (operands[0], operands[1], operands[1], + insn = gen_altivec_vsldoi_ (operands[0], zero_reg, operands[1], shift); } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3029c6f127cd..b5a53a305b94 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2015-08-27 Pat Haugen + + Backport from mainline: + 2015-08-27 Pat Haugen + + * gcc.target/powerpc/vec-shr.c: New. + 2015-08-24 Michael Meissner Backport from mainline: diff --git a/gcc/testsuite/gcc.target/powerpc/vec-shr.c b/gcc/testsuite/gcc.target/powerpc/vec-shr.c new file mode 100644 index 000000000000..31a27c8832dd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-shr.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -fno-inline" } */ + +#include + +typedef struct { double r, i; } complex; +#define LEN 30 +complex c[LEN]; +double d[LEN]; + +void +foo (complex *c, double *d, int len1) +{ + int i; + for (i = 0; i < len1; i++) + { + c[i].r = d[i]; + c[i].i = 0.0; + } +} + +int +main (void) +{ + int i; + for (i = 0; i < LEN; i++) + d[i] = (double) i; + foo (c, d, LEN); + for (i=0;i