From: Teresa Remmet <t.remmet@phytec.de>
Date: Wed, 1 Oct 2025 12:43:28 +0000 (+0200)
Subject: arm64: dts: imx8mm-phygate-tauri-l: Update pad ctl for USB OC pin
X-Git-Tag: v6.19-rc1~100^2~20^2~102
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=052290cdea512d06ad98810df64f253831e79eb9;p=thirdparty%2Fkernel%2Flinux.git

arm64: dts: imx8mm-phygate-tauri-l: Update pad ctl for USB OC pin

Disable Hysteresis Enable Field in pad ctl register for USB OC pin
as this is more appropriate for the signal form in our case.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts
index 755cf9cacd227..2ecc8b3c67dab 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts
@@ -452,7 +452,7 @@
 
 	pinctrl_usbotg1: usbotg1grp {
 		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x80
+			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x00
 		>;
 	};