From: Bjørn Mork Date: Wed, 4 Feb 2026 11:23:24 +0000 (+0100) Subject: realtek: mdio: rtl838x: re-enable phy control via SoC X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=054785b161cd410365c307a44579bfe545e981a1;p=thirdparty%2Fopenwrt.git realtek: mdio: rtl838x: re-enable phy control via SoC Commit 17f12695d083 ("realtek: mdio: rtl838x: activate combo PHY media detection") dropped setting bit 15 of the SMI_GLB_CTRL register without any explanation. This broke the Netgear GS108Tv3, causing phy patching to fail: Firmware loaded. Size 1184, magic: 83808380 Realtek RTL8218B (internal) 1b000000.switchcore:mdio-controller-mii:08: patch Realtek RTL8218B (internal) 1b000000.switchcore:mdio-controller-mii:08: package not ready for patch. Realtek RTL8218B (internal) 1b000000.switchcore:mdio-controller-mii:0f: probe with driver Realtek RTL8218B (internal) failed with error -5 None of the internal phys was able to detect a link after this error. Some rtl8380 devices, like the Zyxel GS1900-10HP A1, were not affected by the bug because their boot loader always sets bit 15. The bug could also be worked around on affected devices by running "rtk network on" before booting OpenWrt, setting bit 15 as a side effect. Cc: Markus Stockhausen Cc: Robert Marko Fixes: 17f12695d083 ("realtek: mdio: rtl838x: activate combo PHY media detection") Signed-off-by: Bjørn Mork Link: https://github.com/openwrt/openwrt/pull/21868 Signed-off-by: Robert Marko --- diff --git a/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c b/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c index 76a61f6f239..e4a7ef49a36 100644 --- a/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c +++ b/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c @@ -666,6 +666,11 @@ static int rtmdio_838x_reset(struct mii_bus *bus) combo_phy = ctrl->smi_bus[24] < 0 ? 0 : BIT(7); regmap_update_bits(ctrl->map, RTMDIO_838X_SMI_GLB_CTRL, BIT(7), combo_phy); + /* + * Bit 15, PHY_PATCH_DONE, enables phy control via SoC. This is required for phy + * access, including patching. Must always be set before the phys are probed. + */ + regmap_update_bits(ctrl->map, RTMDIO_838X_SMI_GLB_CTRL, BIT(15), BIT(15)); return 0; }