From: Robin Dapp <rdapp@ventanamicro.com>
Date: Tue, 5 Dec 2023 14:24:12 +0000 (+0100)
Subject: RISC-V: Add vec_init expander for masks [PR112854].
X-Git-Tag: basepoints/gcc-15~3928
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=056cce412862f8d9b56a40dfbcbc3f9fa7f92883;p=thirdparty%2Fgcc.git

RISC-V: Add vec_init expander for masks [PR112854].

PR112854 shows a problem on rv32 with zvl1024b.  During the course of
expand_constructor we try to overlay/subreg a 64-element mask by a
scalar (Pmode) register.  This works for zvl512b and its maximum of
32 elements but fails for rv32 and 64 elements.

To circumvent this this patch adds a vec_init expander for vector masks
by initializing a QImode vector and comparing that against 0.

gcc/ChangeLog:

	PR target/112854
	PR target/112872

	* config/riscv/autovec.md (vec_init<mode>qi): New expander.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr112854.c: New test.
	* gcc.target/riscv/rvv/autovec/pr112872.c: New test.
---

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index b9f7aa204daf..55d3ae50c8b1 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -394,6 +394,22 @@
   }
 )
 
+;; Provide a vec_init for mask registers by initializing
+;; a QImode vector and comparing it against 0.
+(define_expand "vec_init<mode>qi"
+  [(match_operand:VB 0 "register_operand")
+   (match_operand 1 "")]
+  "TARGET_VECTOR"
+  {
+    machine_mode qimode = riscv_vector::get_vector_mode
+	(QImode, GET_MODE_NUNITS (<MODE>mode)).require ();
+    rtx tmp = gen_reg_rtx (qimode);
+    riscv_vector::expand_vec_init (tmp, operands[1]);
+    riscv_vector::expand_vec_cmp (operands[0], NE, tmp, CONST0_RTX (qimode));
+    DONE;
+  }
+)
+
 ;; Slide an RVV vector left and insert a scalar into element 0.
 (define_expand "vec_shl_insert_<mode>"
   [(match_operand:VI 0 "register_operand")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c
new file mode 100644
index 000000000000..8f7f13f9dc10
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+short a, b;
+void c(int d) {
+  for (; a; a--) {
+    b = 0;
+    for (; b <= 8; b++)
+      if (d)
+        break;
+  }
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c
new file mode 100644
index 000000000000..5c1d2188e127
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */
+
+int a, c;
+char b;
+short d;
+void e() {
+  for (; d; d++) {
+    for (; c;)
+      ;
+    b = 3;
+    for (; b; b = 0)
+      if (a)
+        break;
+  }
+}