From: Tom Hughes <tom@compton.nu>
Date: Fri, 2 Jan 2009 11:03:55 +0000 (+0000)
Subject: Remove spurious newlines from messages.
X-Git-Tag: svn/VALGRIND_3_4_0~8
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0572db7bf5961455598f7c9c32db7ea0dcdf06df;p=thirdparty%2Fvalgrind.git

Remove spurious newlines from messages.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@8890
---

diff --git a/cachegrind/cg-amd64.c b/cachegrind/cg-amd64.c
index 42dbc55834..9415875faf 100644
--- a/cachegrind/cg-amd64.c
+++ b/cachegrind/cg-amd64.c
@@ -144,21 +144,21 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c)
       case 0x48:
          /* Real L2 cache configuration is:
             *L2c = (cache_t) { 3072, 12, 64 }; L2_found = True; */
-         VG_(message)(Vg_DebugMsg, "warning: 3Mb L2 cache detected, treating as 2Mb\n");
+         VG_(message)(Vg_DebugMsg, "warning: 3Mb L2 cache detected, treating as 2Mb");
          *L2c = (cache_t) { 2048, 8, 64 }; L2_found = True;
          break;
       case 0x49:
 	  if ((family == 15) && (model == 6))
 	      /* On Xeon MP (family F, model 6), this is for L3 */
 	      VG_(message)(Vg_DebugMsg, 
-			   "warning: L3 cache detected but ignored\n");
+			   "warning: L3 cache detected but ignored");
 	  else
 	      *L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
 	  break;
       case 0x4e:
          /* Real L2 cache configuration is:
             *L2c = (cache_t) { 6144, 24, 64 }; L2_found = True; */
-         VG_(message)(Vg_DebugMsg, "warning: 6Mb L2 cache detected, treating as 4Mb\n");
+         VG_(message)(Vg_DebugMsg, "warning: 6Mb L2 cache detected, treating as 4Mb");
          *L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
          break;
 
@@ -304,7 +304,7 @@ Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* L2c)
    vendor_id[12] = '\0';
 
    if (0 == level) {
-      VG_(message)(Vg_DebugMsg, "CPUID level is 0, early Pentium?\n");
+      VG_(message)(Vg_DebugMsg, "CPUID level is 0, early Pentium?");
       return -1;
    }
 
diff --git a/cachegrind/cg-x86.c b/cachegrind/cg-x86.c
index 0fe048975b..7480dd5705 100644
--- a/cachegrind/cg-x86.c
+++ b/cachegrind/cg-x86.c
@@ -144,21 +144,21 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c)
       case 0x48:
          /* Real L2 cache configuration is:
             *L2c = (cache_t) { 3072, 12, 64 }; L2_found = True; */
-         VG_(message)(Vg_DebugMsg, "warning: 3Mb L2 cache detected, treating as 2Mb\n");
+         VG_(message)(Vg_DebugMsg, "warning: 3Mb L2 cache detected, treating as 2Mb");
          *L2c = (cache_t) { 2048, 8, 64 }; L2_found = True;
          break;
       case 0x49:
 	  if ((family == 15) && (model == 6))
 	      /* On Xeon MP (family F, model 6), this is for L3 */
 	      VG_(message)(Vg_DebugMsg, 
-			   "warning: L3 cache detected but ignored\n");
+			   "warning: L3 cache detected but ignored");
 	  else
 	      *L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
 	  break;
       case 0x4e:
          /* Real L2 cache configuration is:
             *L2c = (cache_t) { 6144, 24, 64 }; L2_found = True; */
-         VG_(message)(Vg_DebugMsg, "warning: 6Mb L2 cache detected, treating as 4Mb\n");
+         VG_(message)(Vg_DebugMsg, "warning: 6Mb L2 cache detected, treating as 4Mb");
          *L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
          break;
 
@@ -304,7 +304,7 @@ Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* L2c)
    vendor_id[12] = '\0';
 
    if (0 == level) {
-      VG_(message)(Vg_DebugMsg, "CPUID level is 0, early Pentium?\n");
+      VG_(message)(Vg_DebugMsg, "CPUID level is 0, early Pentium?");
       return -1;
    }