From: Chris Metcalf <cmetcalf@ezchip.com>
Date: Wed, 28 Jan 2015 19:51:21 +0000 (-0500)
Subject: tilegx32: set __HAVE_64B_ATOMICS to 0
X-Git-Tag: glibc-2.21~13
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=06991eb816c935961584eeba121e8930c036372f;p=thirdparty%2Fglibc.git

tilegx32: set __HAVE_64B_ATOMICS to 0

This is because of alignment issues in the sem_t support.
tilegx32 does in fact support 64-bit atomics and we will need
to revisit this after the 2.21 freeze.
---

diff --git a/ChangeLog b/ChangeLog
index 1a7d5190398..508f5196daf 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2015-01-28  Chris Metcalf  <cmetcalf@ezchip.com>
+
+	* sysdeps/tile/tilegx/bits/atomic.h [!_LP64] (__HAVE_64B_ATOMICS):
+	Define to 0.
+
 2015-01-28  Joseph Myers  <joseph@codesourcery.com>
 
 	* sysdeps/mips/bits/atomic.h [_MIPS_SIM == _ABIN32]
diff --git a/sysdeps/tile/tilegx/bits/atomic.h b/sysdeps/tile/tilegx/bits/atomic.h
index ac654b8946b..e75efb1c414 100644
--- a/sysdeps/tile/tilegx/bits/atomic.h
+++ b/sysdeps/tile/tilegx/bits/atomic.h
@@ -21,7 +21,15 @@
 
 #include <arch/spr_def.h>
 
-#define __HAVE_64B_ATOMICS 1
+#ifdef _LP64
+# define __HAVE_64B_ATOMICS 1
+#else
+/* tilegx32 does have 64-bit atomics, but assumptions in the semaphore
+   code mean that unaligned 64-bit atomics will be used if this symbol
+   is true, and unaligned atomics are not supported on tile.  */
+# define __HAVE_64B_ATOMICS 0
+#endif
+
 #define USE_ATOMIC_COMPILER_BUILTINS 0
 
 /* Pick appropriate 8- or 4-byte instruction. */