From: Tomoya MORINAGA Date: Fri, 9 Dec 2011 04:13:28 +0000 (+0900) Subject: spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control X-Git-Tag: v3.3.7~4 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=06dd28fc316fa8a8627c0271d24e1d68b51ca6a3;p=thirdparty%2Fkernel%2Fstable.git spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control commit f258b44e22e07f5e98ac2260c70acff5784791b6 upstream. This patch supports a spi mode setup and bit order setup by IO control. spi mode: mode 0 to mode 3 bit order: LSB first, MSB first Signed-off-by: Tomoya MORINAGA Signed-off-by: Grant Likely Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c index 6d0c238a370c0..9f1241dd569e0 100644 --- a/drivers/spi/spi-topcliff-pch.c +++ b/drivers/spi/spi-topcliff-pch.c @@ -1434,6 +1434,7 @@ static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev) master->num_chipselect = PCH_MAX_CS; master->setup = pch_spi_setup; master->transfer = pch_spi_transfer; + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; data->board_dat = board_dat; data->plat_dev = plat_dev;