From: Bill Schmidt Date: Mon, 13 Oct 2014 02:35:03 +0000 (+0000) Subject: backport: rs6000-c.c (altivec_resolve_overloaded_builtin): Issue a warning message... X-Git-Tag: releases/gcc-4.8.4~175 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=06e637fec40a34ee186f3347aca9fa8b7a1f10e6;p=thirdparty%2Fgcc.git backport: rs6000-c.c (altivec_resolve_overloaded_builtin): Issue a warning message when vec_lvsl or vec_lvsr is used with a little endian... [gcc] 2014-10-12 Bill Schmidt Backport from mainline r215880 2014-10-03 Bill Schmidt * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Issue a warning message when vec_lvsl or vec_lvsr is used with a little endian target. Backport from mainline r215882 2014-10-03 Bill Schmidt * altivec.md (altivec_lvsl): New define_expand. (altivec_lvsl_direct): Rename define_insn from altivec_lvsl. (altivec_lvsr): New define_expand. (altivec_lvsr_direct): Rename define_insn from altivec_lvsr. * rs6000.c (rs6000_expand_builtin): Change to use altivec_lvs[lr]_direct; remove commented-out code. [gcc/testsuite] 2014-10-12 Bill Schmidt Backport from mainline r215880 2014-10-03 Bill Schmidt * g++.dg/ext/altivec-2.C: Compile with -Wno-deprecated to avoid failing with the new warning message. * gcc.dg/vmx/3c-01a.c: Likewise. * gcc.dg/vmx/ops-long-1.c: Likewise. * gcc.dg/vmx/ops.c: Likewise. * gcc.target/powerpc/altivec-20.c: Likewise. * gcc.target/powerpc/altivec-6.c: Likewise. * gcc.target/powerpc/altivec-vec-merge.c: Likewise. * gcc.target/powerpc/vsx-builtin-8.c: Likewise. * gcc.target/powerpc/warn-lvsl-lvsr.c: New test. Backport from mainline r215882 2014-10-03 Bill Schmidt * gcc.target/powerpc/lvsl-lvsr.c: New test. Backport from mainline r216017 2014-10-08 Pat Haugen * gcc.dg/vmx/3c-01a.c: Add default options from vmx.exp. * gcc.dg/vmx/ops.c: Likewise. * gcc.dg/vmx/ops-long-1.c: Likewise. From-SVN: r216135 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e7dc0f3e2f76..16541a88bd32 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,22 @@ +2014-10-12 Bill Schmidt + + Backport from mainline r215880 + 2014-10-03 Bill Schmidt + + * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): + Issue a warning message when vec_lvsl or vec_lvsr is used with a + little endian target. + + Backport from mainline r215882 + 2014-10-03 Bill Schmidt + + * altivec.md (altivec_lvsl): New define_expand. + (altivec_lvsl_direct): Rename define_insn from altivec_lvsl. + (altivec_lvsr): New define_expand. + (altivec_lvsr_direct): Rename define_insn from altivec_lvsr. + * rs6000.c (rs6000_expand_builtin): Change to use + altivec_lvs[lr]_direct; remove commented-out code. + 2014-10-09 Uros Bizjak Backport from mainline diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 6abb4feb5eb6..47a4610b78af 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2297,7 +2297,31 @@ "dststt %0,%1,%2" [(set_attr "type" "vecsimple")]) -(define_insn "altivec_lvsl" +(define_expand "altivec_lvsl" + [(use (match_operand:V16QI 0 "register_operand" "")) + (use (match_operand:V16QI 1 "memory_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_lvsl_direct (operands[0], operands[1])); + else + { + int i; + rtx mask, perm[16], constv, vperm; + mask = gen_reg_rtx (V16QImode); + emit_insn (gen_altivec_lvsl_direct (mask, operands[1])); + for (i = 0; i < 16; ++i) + perm[i] = GEN_INT (i); + constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)); + constv = force_reg (V16QImode, constv); + vperm = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, mask, mask, constv), + UNSPEC_VPERM); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], vperm)); + } + DONE; +}) + +(define_insn "altivec_lvsl_direct" [(set (match_operand:V16QI 0 "register_operand" "=v") (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "Z")] UNSPEC_LVSL))] @@ -2305,7 +2329,31 @@ "lvsl %0,%y1" [(set_attr "type" "vecload")]) -(define_insn "altivec_lvsr" +(define_expand "altivec_lvsr" + [(use (match_operand:V16QI 0 "register_operand" "")) + (use (match_operand:V16QI 1 "memory_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_lvsr_direct (operands[0], operands[1])); + else + { + int i; + rtx mask, perm[16], constv, vperm; + mask = gen_reg_rtx (V16QImode); + emit_insn (gen_altivec_lvsr_direct (mask, operands[1])); + for (i = 0; i < 16; ++i) + perm[i] = GEN_INT (i); + constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)); + constv = force_reg (V16QImode, constv); + vperm = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, mask, mask, constv), + UNSPEC_VPERM); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], vperm)); + } + DONE; +}) + +(define_insn "altivec_lvsr_direct" [(set (match_operand:V16QI 0 "register_operand" "=v") (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "Z")] UNSPEC_LVSR))] diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 08ea5c585fd2..3009f1ea80e3 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -4185,6 +4185,14 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, if (TARGET_DEBUG_BUILTIN) fprintf (stderr, "altivec_resolve_overloaded_builtin, code = %4d, %s\n", (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl))); + + /* vec_lvsl and vec_lvsr are deprecated for use with LE element order. */ + if (fcode == ALTIVEC_BUILTIN_VEC_LVSL && !VECTOR_ELT_ORDER_BIG) + warning (OPT_Wdeprecated, "vec_lvsl is deprecated for little endian; use \ +assignment for unaligned loads and stores"); + else if (fcode == ALTIVEC_BUILTIN_VEC_LVSR && !VECTOR_ELT_ORDER_BIG) + warning (OPT_Wdeprecated, "vec_lvsr is deprecated for little endian; use \ +assignment for unaligned loads and stores"); /* For now treat vec_splats and vec_promote as the same. */ if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index ed2df70a61ec..9589d4111363 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -13811,8 +13811,8 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, case ALTIVEC_BUILTIN_MASK_FOR_LOAD: case ALTIVEC_BUILTIN_MASK_FOR_STORE: { - int icode = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr - : (int) CODE_FOR_altivec_lvsl); + int icode = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct + : (int) CODE_FOR_altivec_lvsl_direct); enum machine_mode tmode = insn_data[icode].operand[0].mode; enum machine_mode mode = insn_data[icode].operand[1].mode; tree arg; @@ -13840,7 +13840,6 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) target = gen_reg_rtx (tmode); - /*pat = gen_altivec_lvsr (target, op);*/ pat = GEN_FCN (icode) (target, op); if (!pat) return 0; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 65509575ed24..2608e96dd45f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,31 @@ +2014-10-12 Bill Schmidt + + Backport from mainline r215880 + 2014-10-03 Bill Schmidt + + * g++.dg/ext/altivec-2.C: Compile with -Wno-deprecated to avoid + failing with the new warning message. + * gcc.dg/vmx/3c-01a.c: Likewise. + * gcc.dg/vmx/ops-long-1.c: Likewise. + * gcc.dg/vmx/ops.c: Likewise. + * gcc.target/powerpc/altivec-20.c: Likewise. + * gcc.target/powerpc/altivec-6.c: Likewise. + * gcc.target/powerpc/altivec-vec-merge.c: Likewise. + * gcc.target/powerpc/vsx-builtin-8.c: Likewise. + * gcc.target/powerpc/warn-lvsl-lvsr.c: New test. + + Backport from mainline r215882 + 2014-10-03 Bill Schmidt + + * gcc.target/powerpc/lvsl-lvsr.c: New test. + + Backport from mainline r216017 + 2014-10-08 Pat Haugen + + * gcc.dg/vmx/3c-01a.c: Add default options from vmx.exp. + * gcc.dg/vmx/ops.c: Likewise. + * gcc.dg/vmx/ops-long-1.c: Likewise. + 2014-10-10 Jakub Jelinek PR fortran/59488 diff --git a/gcc/testsuite/g++.dg/ext/altivec-2.C b/gcc/testsuite/g++.dg/ext/altivec-2.C index eb8a92942bc8..e14e6f800f78 100644 --- a/gcc/testsuite/g++.dg/ext/altivec-2.C +++ b/gcc/testsuite/g++.dg/ext/altivec-2.C @@ -1,6 +1,6 @@ /* { dg-do compile { target powerpc*-*-* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ -/* { dg-options "-maltivec -Wall -Wno-unused-but-set-variable" } */ +/* { dg-options "-maltivec -Wall -Wno-unused-but-set-variable -Wno-deprecated" } */ /* This test checks if AltiVec builtins accept const-qualified arguments. */ diff --git a/gcc/testsuite/gcc.dg/vmx/3c-01a.c b/gcc/testsuite/gcc.dg/vmx/3c-01a.c index 2499ca66598c..56f3c8708b82 100644 --- a/gcc/testsuite/gcc.dg/vmx/3c-01a.c +++ b/gcc/testsuite/gcc.dg/vmx/3c-01a.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mno-vsx -Wno-deprecated" } */ #include typedef const volatile unsigned int _1; typedef const unsigned int _2; diff --git a/gcc/testsuite/gcc.dg/vmx/ops-long-1.c b/gcc/testsuite/gcc.dg/vmx/ops-long-1.c index 5471706790ab..bceb4fc8dae9 100644 --- a/gcc/testsuite/gcc.dg/vmx/ops-long-1.c +++ b/gcc/testsuite/gcc.dg/vmx/ops-long-1.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mno-vsx -Wno-deprecated" } */ /* Checks from the original ops.c that pass pointers to long or unsigned long for operations that support that in released versions diff --git a/gcc/testsuite/gcc.dg/vmx/ops.c b/gcc/testsuite/gcc.dg/vmx/ops.c index b39ad1d6569c..21801ca237a2 100644 --- a/gcc/testsuite/gcc.dg/vmx/ops.c +++ b/gcc/testsuite/gcc.dg/vmx/ops.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mno-vsx -Wno-deprecated" } */ #include #include extern char * *var_char_ptr; diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-20.c b/gcc/testsuite/gcc.target/powerpc/altivec-20.c index b2c29a979d92..1af8ed7dc544 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-20.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-20.c @@ -1,5 +1,5 @@ /* { dg-do compile { target powerpc_altivec_ok } } */ -/* { dg-options "-maltivec -mcpu=G5 -O2" } */ +/* { dg-options "-maltivec -mcpu=G5 -O2 -Wno-deprecated" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-6.c b/gcc/testsuite/gcc.target/powerpc/altivec-6.c index 51d411688fb5..29856fd0794b 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-6.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-6.c @@ -1,6 +1,6 @@ /* { dg-do compile { target powerpc*-*-* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ -/* { dg-options "-maltivec -O0 -Wall" } */ +/* { dg-options "-maltivec -O0 -Wall -Wno-deprecated" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c b/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c index 3689f97490ce..b1ed8b864916 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c @@ -1,7 +1,7 @@ /* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ /* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ -/* { dg-options "-maltivec -O2" } */ +/* { dg-options "-maltivec -O2 -Wno-deprecated" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c b/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c new file mode 100644 index 000000000000..71dd0a24ae15 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c @@ -0,0 +1,21 @@ +/* Test expected code generation for lvsl and lvsr on little endian. + Note that lvsl and lvsr are each produced once, but the filename + causes them to appear twice in the file. */ + +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-options "-O0 -Wno-deprecated" } */ +/* { dg-final { scan-assembler-times "lvsl" 2 } } */ +/* { dg-final { scan-assembler-times "lvsr" 2 } } */ +/* { dg-final { scan-assembler-times "lxvd2x" 2 } } */ +/* { dg-final { scan-assembler-times "vperm" 2 } } */ + + +#include + +float f[20]; + +void foo () +{ + vector unsigned char a = vec_lvsl (4, f); + vector unsigned char b = vec_lvsr (8, f); +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c index 836b3851cad8..934cdad250c5 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-options "-O3 -mcpu=power7" } */ +/* { dg-options "-O3 -mcpu=power7 -Wno-deprecated" } */ /* Test the various load/store varients. */ diff --git a/gcc/testsuite/gcc.target/powerpc/warn-lvsl-lvsr.c b/gcc/testsuite/gcc.target/powerpc/warn-lvsl-lvsr.c new file mode 100644 index 000000000000..bf889aaa22b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/warn-lvsl-lvsr.c @@ -0,0 +1,14 @@ +/* Test for deprecation messages on use of lvsl and lvsr for little endian. */ + +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-options "-O0 -Wdeprecated" } */ + +#include + +float f[20]; + +void foo () +{ + vector unsigned char a = vec_lvsl (4, f); /* { dg-warning "vec_lvsl is deprecated for little endian; use assignment for unaligned loads and stores" } */ + vector unsigned char b = vec_lvsr (8, f); /* { dg-warning "vec_lvsr is deprecated for little endian; use assignment for unaligned loads and stores" } */ +}