From: Raghu H Date: Fri, 21 Apr 2023 13:45:07 +0000 (+0100) Subject: docs/cxl: Replace unsupported AARCH64 with x86_64 X-Git-Tag: v8.1.0-rc0~110^2~34 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=0795b98f096b876a36e2c45adb42c2004655011e;p=thirdparty%2Fqemu.git docs/cxl: Replace unsupported AARCH64 with x86_64 Currently Qemu CXL emulation support is not availabe on AARCH64 but its available with qemu x86_64 architecture, updating the document to reflect the supported platform. Signed-off-by: Raghu H Signed-off-by: Jonathan Cameron Message-Id: <20230421134507.26842-4-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index dd1a62bd574..8f2885aba18 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -302,7 +302,7 @@ Example command lines --------------------- A very simple setup with just one directly attached CXL Type 3 device:: - qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \ + qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \ ... -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M \ -object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M \ @@ -315,7 +315,7 @@ A setup suitable for 4 way interleave. Only one fixed window provided, to enable interleave across 2 CXL host bridges. Each host bridge has 2 CXL Root Ports, with the CXL Type3 device directly attached (no switches).:: - qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \ + qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \ ... -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M \ -object memory-backend-file,id=cxl-mem2,share=on,mem-path=/tmp/cxltest2.raw,size=256M \ @@ -339,7 +339,7 @@ the CXL Type3 device directly attached (no switches).:: An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: - qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \ + qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \ ... -object memory-backend-file,id=cxl-mem0,share=on,mem-path=/tmp/cxltest.raw,size=256M \ -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest1.raw,size=256M \