From: Ahmed, Muhammad Date: Tue, 13 Aug 2024 21:11:55 +0000 (-0400) Subject: drm/amd/display: guard write a 0 post_divider value to HW X-Git-Tag: v6.11.3~267 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=081c09301b98b9e4cc0fbb50914b37d086652368;p=thirdparty%2Fkernel%2Fstable.git drm/amd/display: guard write a 0 post_divider value to HW [ Upstream commit 5d666496c24129edeb2bcb500498b87cc64e7f07 ] [why] post_divider_value should not be 0. Reviewed-by: Charlene Liu Signed-off-by: Ahmed, Muhammad Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index 68cd3258f4a97..a64d8f3ec93a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -47,7 +47,8 @@ static void dccg35_trigger_dio_fifo_resync(struct dccg *dccg) uint32_t dispclk_rdivider_value = 0; REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, &dispclk_rdivider_value); - REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value); + if (dispclk_rdivider_value != 0) + REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value); } static void dcn35_set_dppclk_enable(struct dccg *dccg,